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Tue, 20 Feb 2024 14:57:38 -0800 (PST) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id q8-20020a2e9688000000b002d24de76dffsm277990lji.100.2024.02.20.14.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 14:57:37 -0800 (PST) From: Dmitry Baryshkov Subject: [PATCH RESEND 0/2] ARM: implement cacheinfo support (for v7/v7m) Date: Wed, 21 Feb 2024 00:57:35 +0200 Message-Id: <20240221-armv7-cacheinfo-v1-0-69dbd7f20d04@linaro.org> MIME-Version: 1.0 To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZbnkF096dvQGlLCSukEfSJ0VKpmFN+Kk69iSZdj9Crk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBl1S5hN0FsuxyFwjzL6x7MI/ivbGR85lrPsIrSp S5QDh93T7CJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZdUuYQAKCRCLPIo+Aiko 1XOfCACpxpi1idAk+77Rs9FS8U5HnXJ0NyJvUgQdYHU+GbAj9wFeaC+3w3YAbP8HuEx8+Lmg+pT ujIdcaG7dwNygE5zVtjCPFbpI7TXEgMMcQi8iTIeo/vaVlqTwY8Hf7UVAt8CFmLQ+bLnEPZBIwZ cYRdubTJUBw2dSZ6cRlRGOHju3wzv+BH3+rH7MtCUm82wekzeYoF2dSf+5Ju6oSRz7zZujRlgM5 v3KRMBNIDfeX4t20lAqXvubJFK/AHa0kVjci8sAJCE1BuTBF7lsKWN14f0qWVw04o3jIQAzYBR+ 6DsoSln8ROosyCKvUHBab1VhF001tHtCU+fPXJZbOq0VGaBq X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240220_145740_802270_56E37CBF X-CRM114-Status: GOOD ( 10.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Follow the ARM64 platform and implement simple cache information driver. As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is limited to the ARMv7 / ARMv7M, providing simple fallback or just returning -EOPNOTSUPP in case of older platforms. In theory we should be able to skip CLIDR reading and assume that Dcache and Icache (or unified L1 cache) always exist if CTR is supported and returns sensible value. However I think this better be handled by the maintainers of corresponding platforms. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (2): ARM: add CLIDR accessor functions ARM: implement cacheinfo support arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/include/asm/cachetype.h | 13 ++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 164 +++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 6 files changed, 186 insertions(+), 1 deletion(-) --- base-commit: 39676dfe52331dba909c617f213fdb21015c8d10 change-id: 20231231-armv7-cacheinfo-9fa533ae371e Best regards,