From patchwork Mon Mar 4 11:15:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruidong Tian X-Patchwork-Id: 13580451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BCB6C5478C for ; Mon, 4 Mar 2024 11:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=RIiyaCaqQXVyY7gK+M071ycP3Rne2fs3owNnYkgHtZ0=; b=D/E9Gttz8PyfgA zTEJi93am8bBg2xI1suim4jqQO7ML6h5fb2IDU5QTQVTdII/JPGEKFQpgZVc8QPTyY1k0WI82Hpvx L3T3eLeYsN84Q8m9/KQiAjnb/obLOsNjLWEzecmto+mx8V0tX4SsjzVDosDdkW2N4BcRCyAXrkOZh La9gsoqyONkkrg0ptWGnwWjXNoRlrSpoOn5rbZ02ZK8L+q7Izmh3wmxDb6Rt7xYzzjek4AL3HlnZv 2JyO/PYht/jKL5AkN1DqTxKD1z9FufOoyED2KlUhOzIGilTqP/70djcSMNLfKHrTDXBmti/Pw78mE 448WXbWXNOTbHcLIerkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rh6I9-00000008mN6-1qgY; Mon, 04 Mar 2024 11:15:33 +0000 Received: from out30-111.freemail.mail.aliyun.com ([115.124.30.111]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rh6I6-00000008mKj-1Fh1 for linux-arm-kernel@lists.infradead.org; Mon, 04 Mar 2024 11:15:32 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1709550923; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=+KToDONWSyU96YdlBLNtPCPCwLodjffJBV7loL7KhQU=; b=PaH+OBrmzYnissYEeSfw0KIhDFF6nxnIY+taWQHGwvPCywkWq4WdtCLOo9mVNZI3FNe0Sl1162El4rFRDX7RXgBuk4mn7hGKK9UT7l8ppCnT8B7Zlr79AlXou9WMvAwSlGU7AsU9TRxTQmbSBeSwaMeQ2hwu+6B0i+G4crOtHy4= X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R691e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=tianruidong@linux.alibaba.com;NM=1;PH=DS;RN=11;SR=0;TI=SMTPD_---0W1oM1bh_1709550918; Received: from localhost(mailfrom:tianruidong@linux.alibaba.com fp:SMTPD_---0W1oM1bh_1709550918) by smtp.aliyun-inc.com; Mon, 04 Mar 2024 19:15:21 +0800 From: Ruidong Tian To: catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com, xueshuai@linux.alibaba.com, baolin.wang@linux.alibaba.com, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Ruidong Tian Subject: [PATCH 0/2] ARM Error Source Table V1 Support Date: Mon, 4 Mar 2024 19:15:15 +0800 Message-Id: <20240304111517.33001-1-tianruidong@linux.alibaba.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240304_031530_737117_D1B20099 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the ARM Error Source Table (AEST) based on the 1.1 version of ACPI for the Armv8 RAS Extensions [0]. The Arm Error Source Table (AEST) enable kernel-first handling of errors in a system that supports the Armv8 RAS extensions. Hardware errors will trigger a RAS interrupt to kernel, kernel scan all AEST node to fine error node which occur error in irq context and use a workqueue to log this hardware errors. I have tested this series on PTG Yitian710 SOC. Both corrected and uncorrected errors were tested to verify the non-fatal vs fatal scenarios. Future work: 1. UE trigger memory_failure other than panic. 2. Add CE storm mitigation. 3. Support AEST V2. This series is based on Tyler Baicar's patches [1], which do not have v2 sended to mail list yet. Change from origin patch: 1. Add a genpool to collect all AEST error, and log them in a workqueue other than in irq context. 2. Just use the same one aest_proc function for system register interface and MMIO interface. 3. Reconstruct some structures and functions to make it more clear. 4. Accept all comments in Tyler Baicar's mail list. [0]: https://developer.arm.com/documentation/den0085/0101/ [1]: https://lore.kernel.org/all/20211124170708.3874-1-baicar@os.amperecomputing.com/ Tyler Baicar (2): ACPI/AEST: Initial AEST driver trace, ras: add ARM RAS extension trace event MAINTAINERS | 11 + arch/arm64/include/asm/ras.h | 38 ++ drivers/acpi/arm64/Kconfig | 10 + drivers/acpi/arm64/Makefile | 1 + drivers/acpi/arm64/aest.c | 728 +++++++++++++++++++++++++++++++++++ include/linux/acpi_aest.h | 91 +++++ include/linux/cpuhotplug.h | 1 + include/ras/ras_event.h | 55 +++ 8 files changed, 935 insertions(+) create mode 100644 arch/arm64/include/asm/ras.h create mode 100644 drivers/acpi/arm64/aest.c create mode 100644 include/linux/acpi_aest.h