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Fri, 29 Mar 2024 23:59:12 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , Dmitry Rokosov Subject: [PATCH v1 0/6] clk: meson: introduce Amlogic A1 SoC Family CPU clock controller driver Date: Fri, 29 Mar 2024 23:58:40 +0300 Message-ID: <20240329205904.25002-1-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Originating-IP: [100.64.160.123] X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 184500 [Mar 29 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 14 0.3.14 5a0c43d8a1c3c0e5b0916cc02a90d4b950c01f96, {Tracking_from_domain_doesnt_match_to}, salutedevices.com:7.1.1;127.0.0.199:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;100.64.160.123:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/03/29 16:52:00 #24511844 X-KSMG-AntiVirus-Status: Clean, skipped X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_135920_979621_D6F336CF X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CPU clock controller plays a general role in the Amlogic A1 SoC family by generating CPU clocks. As an APB slave module, it offers the capability to inherit the CPU clock from two sources: the internal fixed clock known as 'cpu fixed clock' and the external input provided by the A1 PLL clock controller, referred to as 'syspll'. It is important for the driver to handle the cpu_clk rate switching effectively by transitioning to the CPU fixed clock to avoid any potential execution freezes. Validation: * to double-check all clk flags, run the below helper script: ``` pushd /sys/kernel/debug/clk for f in *; do if [[ -f "$f/clk_flags" ]]; then flags="$(cat $f/clk_flags | awk '{$1=$1};1' | sed ':a;N;$!ba;s/\n/ | /g')" echo -e "$f: $flags" fi done popd ``` * to trace the current clks state, use the '/sys/kernel/debug/clk/clk_dump' node with jq post-processing: ``` $ cat /sys/kernel/debug/clk/clk_dump | jq '.' > clk_dump.json ``` * to see the CPU clock hierarchy, use the '/sys/kernel/debug/clk/clk_summary' node with jq post-processing: ``` $ cat /sys/kernel/debug/clk/clk_summary | jq '.' > clk_dump.json ``` when cpu_clk is inherited from sys_pll, it should be: ``` syspll_in 1 1 0 24000000 0 0 50000 Y deviceless no_connection_id sys_pll 2 2 0 1200000000 0 0 50000 Y deviceless no_connection_id cpu_clk 1 1 0 1200000000 0 0 50000 Y cpu0 no_connection_id cpu0 no_connection_id fd000000.clock-controller dvfs deviceless no_connection_id ``` and from cpu fixed clock: ``` fclk_div3_div 1 1 0 512000000 0 0 50000 Y deviceless no_connection_id fclk_div3 4 4 0 512000000 0 0 50000 Y deviceless no_connection_id cpu_fsource_sel0 1 1 0 512000000 0 0 50000 Y deviceless no_connection_id cpu_fsource_div0 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_fsel0 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_fclk 1 1 0 128000000 0 0 50000 Y deviceless no_connection_id cpu_clk 1 1 0 128000000 0 0 50000 Y cpu0 no_connection_id cpu0 no_connection_id fd000000.clock-controller dvfs deviceless no_connection_id ``` * to debug cpu clk rate propagation and proper parent switching, compile kernel with the following definition: $ sed -i "s/undef CLOCK_ALLOW_WRITE_DEBUGFS/define CLOCK_ALLOW_WRITE_DEBUGFS/g" drivers/clk/clk.c after that, clk_rate debug node for each clock will be available for write operation Dmitry Rokosov (6): dt-bindings: clock: meson: a1: pll: introduce new syspll bindings clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock dt-bindings: clock: meson: a1: peripherals: support sys_pll_div16 input clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input dt-bindings: clock: meson: add A1 CPU clock controller bindings clk: meson: a1: add Amlogic A1 CPU clock controller driver .../bindings/clock/amlogic,a1-cpu-clkc.yaml | 64 ++++ .../clock/amlogic,a1-peripherals-clkc.yaml | 5 +- .../bindings/clock/amlogic,a1-pll-clkc.yaml | 7 +- drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-cpu.c | 324 ++++++++++++++++++ drivers/clk/meson/a1-cpu.h | 16 + drivers/clk/meson/a1-peripherals.c | 4 +- drivers/clk/meson/a1-pll.c | 78 +++++ drivers/clk/meson/a1-pll.h | 6 + .../dt-bindings/clock/amlogic,a1-cpu-clkc.h | 19 + .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 2 + 12 files changed, 531 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml create mode 100644 drivers/clk/meson/a1-cpu.c create mode 100644 drivers/clk/meson/a1-cpu.h create mode 100644 include/dt-bindings/clock/amlogic,a1-cpu-clkc.h Reviewed-by: Rob Herring