Message ID | 20240412142702.2882478-1-suzuki.poulose@arm.com (mailing list archive) |
---|---|
Headers | show |
Series | coresight: etm4x: Fix CPU idle PM support for ETE | expand |
On Fri, 12 Apr 2024 15:26:58 +0100, Suzuki K Poulose wrote: > Our CPUidle state save restore has some bugs which are triggered for an ETM with > system instructions (e.g. ETE). This is a series of fixes to address them. > > Changes since v1: > - Fix inverted check for drvdata->csdev for Patch 1 (Yabin) > - Remove Data trace register access macro cases (Mike Leach) > - Fix QFILT field definition (Yabin) > - (New patch) Fix Resource pair register access, reported-by Yabin > > [...] Applied, thanks! [1/4] coresight: etm4x: Do not hardcode IOMEM access for register restore https://git.kernel.org/coresight/c/1e7ba33fa591de1cf60afffcabb45600b3607025 [2/4] coresight: etm4x: Do not save/restore Data trace control registers https://git.kernel.org/coresight/c/5eb3a0c2c52368cb9902e9a6ea04888e093c487d [3/4] coresight: etm4x: Safe access for TRCQCLTR https://git.kernel.org/coresight/c/46bf8d7cd8530eca607379033b9bc4ac5590a0cd [4/4] coresight: etm4x: Fix access to resource selector registers https://git.kernel.org/coresight/c/d6fc00d0f640d6010b51054aa8b0fd191177dbc9 Best regards,