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Mon, 29 Apr 2024 18:20:10 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 17-20020ac24851000000b00518a01fdf2asm4322096lfy.144.2024.04.29.18.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 18:20:09 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH RESEND 0/2] ARM: implement cacheinfo support (for v7/v7m) Date: Tue, 30 Apr 2024 04:20:07 +0300 Message-Id: <20240430-armv7-cacheinfo-v1-0-e3d1caa40dc5@linaro.org> MIME-Version: 1.0 To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZbnkF096dvQGlLCSukEfSJ0VKpmFN+Kk69iSZdj9Crk=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmMEdI5yZ32njDEk3YOGHJxMW03EdEduauAfduV RXmmcrsiZCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZjBHSAAKCRCLPIo+Aiko 1WhyB/9HpnavWmliWCzk//NVD2j75fcriXM8fVHnd7tXMIRj9XgAL9c6oRxj9RFHOe2o0WvCmyN S5lxcycwN7EZ/9c1r7ZJPmleCEqW+/X2HC5G3caPlROjhRuI96pPXRhex950ubRUfZTZg/oV9p0 1xAqOg4lT+TWprIzKz/GneavfN52ZtJJEechQvdHzg9aCr1HEr0pnVG/2CYX/ie2ukrg2QQTfIL hMwMOch0MNL3MiMZnaAq3tBbxiD+E49YMc2utFUCjOQUwtCtVg1+ZgpIKlI0docjL7wN6t53JTo pB9HnPaq6V0B5YMtELEcxbmXxIf1zDkslX/FeT9SI5t8D6iE X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_182014_431120_6BEADB7E X-CRM114-Status: GOOD ( 10.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Follow the ARM64 platform and implement simple cache information driver. As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is limited to the ARMv7 / ARMv7M, providing simple fallback or just returning -EOPNOTSUPP in case of older platforms. In theory we should be able to skip CLIDR reading and assume that Dcache and Icache (or unified L1 cache) always exist if CTR is supported and returns sensible value. However I think this better be handled by the maintainers of corresponding platforms. Signed-off-by: Dmitry Baryshkov --- Dmitry Baryshkov (2): ARM: add CLIDR accessor functions ARM: implement cacheinfo support arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/include/asm/cachetype.h | 13 ++++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 164 +++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 6 files changed, 186 insertions(+), 1 deletion(-) --- base-commit: 39676dfe52331dba909c617f213fdb21015c8d10 change-id: 20231231-armv7-cacheinfo-9fa533ae371e Best regards,