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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-41f88110f3esm32622515e9.29.2024.05.08.12.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 12:19:32 -0700 (PDT) From: Alexandre Ghiti To: Ryan Roberts , Catalin Marinas , Will Deacon , Alexander Potapenko , Marco Elver , Dmitry Vyukov , Paul Walmsley , Palmer Dabbelt , Albert Ou , Ard Biesheuvel , Anup Patel , Atish Patra , Andrey Ryabinin , Andrey Konovalov , Vincenzo Frascino , Andrew Morton , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-riscv@lists.infradead.org, linux-efi@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-mm@kvack.org Cc: Alexandre Ghiti Subject: [PATCH 00/12] Make riscv use THP contpte support for arm64 Date: Wed, 8 May 2024 21:19:19 +0200 Message-Id: <20240508191931.46060-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_121938_122523_7EFD000B X-CRM114-Status: GOOD ( 15.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This allows riscv to support napot (riscv equivalent to contpte) THPs by moving arm64 contpte support into mm, the previous series [1] only merging riscv and arm64 implementations of hugetlbfs contpte. riscv contpte specification allows for different contpte sizes, although only 64KB is supported for now. So in this patchset is implemented the support of multiple contpte sizes, which introduces a few arch specific helpers to determine what sizes are supported. Even though only one size is supported on riscv, the implementation of the multi size support is to show what it will look like when we support other sizes, and make sure it does not regress arm64. I tested arm64 using the cow kselftest and a kernel build with 4KB base page size and 64KB contpte. riscv was tested with the same tests on *all* contpte sizes that fit in the last page table level (support for PMD sizes is not present here). Both arch were only tested on qemu. Alexandre Ghiti (12): mm, arm64: Rename ARM64_CONTPTE to THP_CONTPTE mm, riscv, arm64: Use common ptep_get() function mm, riscv, arm64: Use common set_ptes() function mm, riscv, arm64: Use common ptep_get_lockless() function mm, riscv, arm64: Use common set_pte() function mm, riscv, arm64: Use common pte_clear() function mm, riscv, arm64: Use common ptep_get_and_clear() function mm, riscv, arm64: Use common ptep_test_and_clear_young() function mm, riscv, arm64: Use common ptep_clear_flush_young() function mm, riscv, arm64: Use common ptep_set_access_flags() function mm, riscv, arm64: Use common ptep_set_wrprotect()/wrprotect_ptes() functions mm, riscv, arm64: Use common get_and_clear_full_ptes()/clear_full_ptes() functions arch/arm64/Kconfig | 9 - arch/arm64/include/asm/pgtable.h | 318 +++++--------- arch/arm64/mm/Makefile | 1 - arch/arm64/mm/contpte.c | 408 ------------------ arch/arm64/mm/hugetlbpage.c | 6 +- arch/arm64/mm/mmu.c | 2 +- arch/riscv/include/asm/kfence.h | 4 +- arch/riscv/include/asm/pgtable.h | 206 +++++++++- arch/riscv/kernel/efi.c | 4 +- arch/riscv/kernel/hibernate.c | 2 +- arch/riscv/kvm/mmu.c | 26 +- arch/riscv/mm/fault.c | 2 +- arch/riscv/mm/init.c | 4 +- arch/riscv/mm/kasan_init.c | 16 +- arch/riscv/mm/pageattr.c | 8 +- arch/riscv/mm/pgtable.c | 6 +- include/linux/contpte.h | 37 ++ mm/Kconfig | 9 + mm/contpte.c | 685 ++++++++++++++++++++++++++++++- 19 files changed, 1056 insertions(+), 697 deletions(-) delete mode 100644 arch/arm64/mm/contpte.c create mode 100644 include/linux/contpte.h