From patchwork Mon May 20 10:11:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: s-vadapalli X-Patchwork-Id: 13668166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA8EBC25B78 for ; Mon, 20 May 2024 10:12:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=J+oSknFY/k0vBXm9YN47i5UJg1TQpWZcaxrpaLUU0iw=; b=P7WvrWoSWnfF1E 9cNvhV+0UiaqjG7zLiWlbiEwxLQtPWz3jZ1402+WR8zrfbT1Lpbh5wLRjPKHpoIc32dqcFqVrppO1 e7sLE4d7m5Cu9F59vk5V+997TcmtEbGmSdq8wnEYktnZj17+ISzI8JP1MKtcgXpe00a09QNEvKGE8 Iz6Qy16ly4PhrpYeBRkxAPZIL+oug0vHvwLC8REyzwKkfcHPLLNLn8zexuI/XqPm0J6fF4ASjyiwU UPY5CtESRhszAsuiHRr2E9NYmnoJX4pD4RNV4wIyxLCbkRwWcYs9QHneXWIxRcifmw8bpj9ZxAxj0 zLV6SMsTJRoOVNJHws2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s900D-0000000E6F5-2uk8; Mon, 20 May 2024 10:12:21 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s9006-0000000E69G-2MfO for linux-arm-kernel@lists.infradead.org; Mon, 20 May 2024 10:12:16 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44KABrbs112056; Mon, 20 May 2024 05:11:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716199913; bh=l9dQQBkoaq18ik/IFSgRjGWwiw8uydoqC4ckZ4WqZ90=; h=From:To:CC:Subject:Date; b=BRKsI0cZq6HCnyscELq36UuCvjbSVyTFhfsbXze2JJOOMDwsMnwzHzishae6f6Gvv O/NsXbH0Jd9ZVRCwV9HANhmb9gQdioX8vBbQRwpnNMQha/5Zn9LPW3qMB4ajhQsCFn mpyB6ZlfwERhWFx+h/aBs2fBBqZLhXBD3Wj9NRR8= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44KABroq025278 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 20 May 2024 05:11:53 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 20 May 2024 05:11:53 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 20 May 2024 05:11:53 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44KABnjS060604; Mon, 20 May 2024 05:11:50 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , , Subject: [PATCH v2 0/3] Add PCIe DT support for TI's J784S4 SoC Date: Mon, 20 May 2024 15:41:46 +0530 Message-ID: <20240520101149.3243151-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240520_031214_779434_39559036 X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello, TI's J784S4 SoC has two Gen3 x4 Lane PCIe Controllers. This series adds the necessary device-tree support to enable both PCIe instances in Root Complex mode of operation by default. The device-tree overlay to enable both instances in Endpoint mode of operation is also present in this series. v1: https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com Changes since v1: - Rebased series on linux-next tagged next-2024020. - All dependencies mentioned in v1 series have been met. This series has no further dependencies for functionality. - Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller node (scm_conf). This enables reusing the existing "ti,syscon-pcie-ctrl" property without having to map the entire System Controller region for configuring the PCIe specific registers within "scm_conf". This change is also done in the "overlay" file in patch 3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl nodes to the "ti,syscon-pcie-ctrl" property in the overlay. Test Logs: 1. PCIe0 and PCIe1 in Root Complex Modes of operation with an NVMe SSD connected to the PCIe0 instance and the Read Performance measured with hdparm command: https://gist.github.com/Siddharth-Vadapalli-at-TI/96c4ca37dd855120516ccdc298548dc6 2. PCIe0 Endpoint Mode functionality verified with the overlay. Logs of the RC enumerating PCIe0 as an Endpoint: https://gist.github.com/Siddharth-Vadapalli-at-TI/01b6fb0c9494ab76607b574a728b84da 3. PCIe1 Endpoint Mode functionality verified with the overlay. Logs of the RC enumerating PCIe1 as an Endpoint: https://gist.github.com/Siddharth-Vadapalli-at-TI/e844ac92d56131cbb2c134fab621b1e6 Regards, Siddharth. Siddharth Vadapalli (3): arm64: dts: ti: k3-j784s4-main: Add PCIe nodes arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode arch/arm64/boot/dts/ti/Makefile | 7 +- .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 +++++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 94 +++++++++++++++++++ 4 files changed, 225 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso