From patchwork Wed May 29 08:22:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13678313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CC5BC25B7C for ; Wed, 29 May 2024 08:23:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=3cIW8QnqHqQmzg+ThIqY4Iq+o8dtv9GrxBTMhV+smGI=; b=as+1te+KHEHRni ieF+/CMg7zYo8Gtl0xkVM4Esjrh5ya5lsuB8Zh2BkyrCEc2fD6pb/9wMN2+mXnF8k9XwBblsCA1gS 2KyzDhgjyO8/++MoO1XdnceREmuroHWOuJ4RFPmpaxQtaAnZjF6b+ACMm6kYvZp2HEMuoCA8LMr9W 3z1TIEbMzMlZp+dXKWy5guM+u/36+77WrkBHN2/G8OCcKoQhX9Cx8ylDaJ3QdN6dki2cY/URWPF5M z95FFItX922qcRJF2Pph42hDcY5IzRMQP5GNLJBQruvjKG63lQvTVqMijR00IgLxt3CTRdX2oEwDY bIY1NmLDKIpIKfR/IYtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCEan-00000003MZj-0fdf; Wed, 29 May 2024 08:23:29 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCEac-00000003MUV-0n9Q for linux-arm-kernel@lists.infradead.org; Wed, 29 May 2024 08:23:22 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44T8N5jP028176; Wed, 29 May 2024 03:23:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1716970985; bh=GA84cJ8nNnm/xjeHKTyGRus4Kr3hXRBkbAwrEXa69NI=; h=From:To:CC:Subject:Date; b=wf5DmHRWdAUIVyzyR3VzxbjbUXqYbnyu5p5it8WEZaNoZjbhR/txYWd4abn8aD6OF /DJb6ncZpbD2OR1OQt/+qOCH0Q+Fban0n4+LE3ba0qNLCXPIlLwqBLC5+BEa1Fie/7 ha6ZHxGXzmMKqS6MbJrRvVOPc/jblFuJyyLeDFoQ= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44T8N5r9048695 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 May 2024 03:23:05 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 29 May 2024 03:23:04 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 29 May 2024 03:23:04 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44T8N0d6084708; Wed, 29 May 2024 03:23:00 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , , , , Subject: [PATCH v4 0/4] Add PCIe DT support for TI's J784S4-EVM and AM69-SK Date: Wed, 29 May 2024 13:52:55 +0530 Message-ID: <20240529082259.1619695-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240529_012318_348190_011A6A58 X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TI's J784S4 SoC has two x4 Lane and two x2 Lane Gen3 PCIe Controllers. This series adds the device-tree nodes for all 4 PCIe instances in the SoC file (k3-j784s4-main.dtsi). The J784S4-EVM board has only PCIe0 and PCIe1 instances of PCIe brought out while the AM69-SK board has PCIe0, PCIe1 and PCIe3 instances of PCIe brought out. The device-tree overlay to enable PCIe0 and PCIe1 in Endpoint mode of operation on J784S4-EVM is also included in this series. v3: https://lore.kernel.org/r/20240523111008.4057988-1-s-vadapalli@ti.com/ Changes since v3: - Rebased on linux-next tagged next-20240528. - Added ranges for PCIe2 and PCIe3 in k3-j784s4.dtsi which was missed in v3 series. - Added new patch in this series for enabling PCIe on AM69-SK board. v2: https://lore.kernel.org/r/20240520101149.3243151-1-s-vadapalli@ti.com/ Changes since v2: - Rebased on linux-next tagged next-20240523. - Based on feedback from Francesco Dolcini at: https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/ the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been added. v1: https://lore.kernel.org/r/20240129114749.1197579-1-s-vadapalli@ti.com Changes since v1: - Rebased series on linux-next tagged next-20240520. - All dependencies mentioned in v1 series have been met. This series has no further dependencies for functionality. - Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller node (scm_conf). This enables reusing the existing "ti,syscon-pcie-ctrl" property without having to map the entire System Controller region for configuring the PCIe specific registers within "scm_conf". This change is also done in the "overlay" file in patch 3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl nodes to the "ti,syscon-pcie-ctrl" property in the overlay. Test Logs: 1. J784S4-EVM PCIe0 and PCIe1 in RC Mode with NVMe SSD connected to PCIe0: https://gist.github.com/Siddharth-Vadapalli-at-TI/af94b2da5dd0613de8a238e37f70eb7e 2. J784S4-EVM PCIe0 as Endpoint and AM69-SK PCIe0 acting as RC: https://gist.github.com/Siddharth-Vadapalli-at-TI/1d305c5145bdc34975615e15fe0f433c 3. J784S4-EVM PCIe1 as Endpoint and AM69-SK PCIe0 acting as RC: https://gist.github.com/Siddharth-Vadapalli-at-TI/3129da32c9984f4f02351ca03105e49e 4. AM69-SK PCIe0, PCIe1 and PCIe3 in RC Mode with NVMe SSD connected to PCIe0: https://gist.github.com/Siddharth-Vadapalli-at-TI/5571eb0a0273501fcc214519beab6713 Regards, Siddharth. Dasnavis Sabiya (1): arm64: dts: ti: k3-am69-sk: Add PCIe support Siddharth Vadapalli (3): arm64: dts: ti: k3-j784s4-main: Add PCIe nodes arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode arch/arm64/boot/dts/ti/Makefile | 7 +- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 60 ++++++++ .../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++ arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 10 +- 6 files changed, 336 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso