From patchwork Mon Jun 3 11:18:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13683670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91C8DC25B76 for ; Mon, 3 Jun 2024 11:18:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=/GRqh8T6Lw87QbCjb7diVPfqGRF9c5Qtn4JvAaR+auE=; b=I65uapJnyrJhdq qRG+GD/RIPiFafEu0tB2dfCG+1ECMXewLYZwIqXrI2p80ht88CYyPMYH1BjBXUF4iseKg5E514nbv BJZYOQePQy/M0IGQ9gFxHy+h9Tm0mBl+r1ST1uMtUrvVrctgb9VatP81/LFTfYVFLW4Nmn4tQP+hj 29U45eFsYRseprdQUPESBDiT/2i5pUVlwnzUrDwwaMJUjnaEQAS+CDZYPHI/NrVyVhWilL/ej/csh /rCx5wHXl4B8KVghth7ydm8utm6ocn8RWZVlntJ91OQYY9jdJyBpnU/X2o4aeNYo6UODajgHcDCFp nPIog/O2NA/yolGI1BXw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sE5hv-0000000GVFW-0D3v; Mon, 03 Jun 2024 11:18:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sE5hq-0000000GVDA-3Gav for linux-arm-kernel@lists.infradead.org; Mon, 03 Jun 2024 11:18:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2772E1042; Mon, 3 Jun 2024 04:18:48 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E674E3F64C; Mon, 3 Jun 2024 04:18:22 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, james.morse@arm.com, mark.rutland@arm.com, will@kernel.org, wilL@kernel.org Subject: [PATCH 0/5] arm64: errata: Expand speculative SSBS workaround Date: Mon, 3 Jun 2024 12:18:07 +0100 Message-Id: <20240603111812.1514101-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240603_041826_962089_A830DA59 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We recently addressed this for Cortex-X4 and Neoverse-V3: https://lore.kernel.org/linux-arm-kernel/20240508081400.235362-1-mark.rutland@arm.com/ ... which was merged into mainline in v6.10-rc1. Since then, Arm have published Software Developer Errata Notice (SDEN) documents for a number of CPUs affected by the same issue. This series updates the workaround to handle those CPUs. Since there are now a number of CPUs known to be affected, I've merged the Kconfig options to avoid duplicate text and boilerplate ifdeffery. Largely this is mechanical work to add the IDs and handle them for detection, but I have made two choices I'd like to check: * For the common Kconfig symbol I've used CONFIG_ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID), following the example of CONFIG_ARM64_ERRATUM_1319367 which covers Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. Given the precedent, I'm assuming that's fine. I also considered ARM64_ERRATUM_SPECULATIVE_SSBS, but that required reflowing the table in the documentation, which is very churny. * I updated the runtime message to say: "SSBS not fully self-synchronizing", ... rather than listing every relevant erratum ID, as this would become very long: "ARM errata 3194386, 3312417, 3324334, 3324335, 3324336, 3324338, 3324339, 3456091" ... and if we end up needing to add more affected CPUs it would get even longer. I'm happy to use the latter if that's preferable. Mark. Mark Rutland (5): arm64: cputype: Add Cortex-X3 definitions arm64: cputype: Add Cortex-A720 definitions arm64: cputype: Add Cortex-X925 definitions arm64: errata: Unify speculative SSBS errata logic arm64: errata: Expand speculative SSBS workaround Documentation/arch/arm64/silicon-errata.rst | 16 ++++++++- arch/arm64/Kconfig | 36 +++++++-------------- arch/arm64/include/asm/cpucaps.h | 2 +- arch/arm64/include/asm/cputype.h | 6 ++++ arch/arm64/kernel/cpu_errata.c | 17 ++++++---- arch/arm64/kernel/proton-pack.c | 2 +- 6 files changed, 44 insertions(+), 35 deletions(-)