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AJvYcCWHS68ZGeotgMNZCuxGavt8UQtUNTjbk3Vof7yrM5XNnMut9XtDfqPEmO+BY32b+P9KaY1Jm9cL5POIDUP5iJ36BpIUMJ3XbTSyAgka0hsrk0vND7OQGCPvzby6zftOn56icrNO8/zFH98V54/oMf1h8bY9N2D16g0= X-Gm-Message-State: AOJu0YwMoApflIqQYRXRIirhjJDMmEjh4Rgu+fPmoPaz2tC3VpE0I9pu gzWcWhgufdD9sfOz547rlY4IN2IAXnc6LEsotDJ0APGKjXhEH6wn X-Google-Smtp-Source: AGHT+IEX+hO1fjOTWqgdmiNAEFg0qrDQFDw6cG1U1FlLDxT3z8cZCdVuh8JspRxuIl3ApF0IENghfA== X-Received: by 2002:a05:6512:3e24:b0:52b:874a:7df with SMTP id 2adb3069b0e04-52b8955c5bfmr9728475e87.12.1717510331074; Tue, 04 Jun 2024 07:12:11 -0700 (PDT) Received: from yoga-710.tas.nnz-ipc.net ([178.218.200.115]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52b982d3de7sm742743e87.2.2024.06.04.07.12.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jun 2024 07:12:10 -0700 (PDT) From: Dmitry Yashin To: Linus Walleij , Heiko Stuebner Cc: Luca Ceresoli , Jianqun Xu , Jonas Karlman , devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dmitry Yashin Subject: [PATCH v3 0/2] pinctrl: rockchip: add rk3308b SoC support Date: Tue, 4 Jun 2024 19:10:18 +0500 Message-ID: <20240604141020.21725-1-dmt.yashin@gmail.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240604_071214_231993_BBE308D2 X-CRM114-Status: GOOD ( 12.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series and adds support for pin controller found on rk3308b. According to rk3308b TRM, this pinctrl much the same as rk3308's, but with additional iomux routes and 3bit iomuxes selected via gpio##_sel_src_ctrl registers. Downstream kernel [1] managed this SoC's with rk3308b_soc_data_init, wich picked configuration based on cpuid. Upstream pinctrl patches droped soc init function. The function rk3308b_soc_sel_src_init sets up gpio##_sel_src_ctrl registers, making SoC to use 3bit iomuxes over some 2bit old ones. These patches have been tested on Radxa's ROCK Pi S, one based on rk3308 and the other on rk3308b (from the latest batches). For the new boards it fixes broken spi1 clk. Similar effort [2] was made several years ago, but without keeping base rk3308 SoC pinctrl support. Based on feedback from Luca, Heiko and Jonas, the v2 series droped dt binding in the favor of runtime SoC detection, so iomux_recalced and iomux_routes updated for the new SoC's and patch 1 delays recalced_mask and route_mask init. [1] https://github.com/radxa/kernel/blob/stable-4.4-rockpis/drivers/pinctrl/pinctrl-rockchip.c#L4388 [2] https://lore.kernel.org/linux-rockchip/20220930102620.1568864-1-jay.xu@rock-chips.com/ v1 Link: https://lore.kernel.org/all/20240515121634.23945-1-dmt.yashin@gmail.com/ v2 Link: https://lore.kernel.org/all/20240529143534.32402-1-dmt.yashin@gmail.com/ Changes in v3: - Witespace cleanup - Add Luca's r-b tag - Rebase onto linux-pinctrl for-next branch Changes in v2: - Drop routes fixup patch, already applied - Drop dt binding patch - Add new patch to delay recalced_mask and route_mask init - Rework last patch from dt to runtime setup with rk3308_soc_data_update Dmitry Yashin (2): pinctrl: rockchip: delay recalced_mask and route_mask init pinctrl: rockchip: add rk3308b SoC support drivers/pinctrl/pinctrl-rockchip.c | 286 +++++++++++++++++++++++++++-- drivers/pinctrl/pinctrl-rockchip.h | 1 + 2 files changed, 267 insertions(+), 20 deletions(-) base-commit: 32335efff386d04961b178d4c6b7d1ccbafb729f