From patchwork Mon Jun 17 11:18:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 13700514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EF75C27C79 for ; Mon, 17 Jun 2024 11:19:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Tt7DClsnFkLDqouUXDg2I3nCUQ0LeszT7GhWayyiUtg=; b=xy32PRjoGCDlwIsqU/mD+iMvLD n1KhQoDZNI5/r4wOldZi/q7eTkWD52x1mSVIMtAeq0Duz4yzIgOrLKXCWrTY2KBDj3i0pd8WWIOrd Xd/f34J9lNz49PF8dIpTYPjF1m5J8YOaVSngqgPL9BaRJ86B06HVXC8YL5q+Y7VUfUxjCJjrRpRo0 C6Wi5Nq4fJGTD0T8sgSP1d9pXjMPKUbxZumGNfYoZd34VJ8RSKjnXWrBrWSnJxBB0/drznYoOdS1L yF1gbUpcLnEzu0FqbOM5RN0lOXV/ZZ3Vg0IS/40F5BOk2Q0xRPvO/xKmdD4JMz5Q8F9hyVZZDQm+y 2tPjozyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJANu-0000000ARMA-3OIz; Mon, 17 Jun 2024 11:18:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJANr-0000000ARLY-1zuu for linux-arm-kernel@lists.infradead.org; Mon, 17 Jun 2024 11:18:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 193ACDA7; Mon, 17 Jun 2024 04:19:11 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5DCE43F6A8; Mon, 17 Jun 2024 04:18:45 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Thomas Gleixner , Will Deacon Cc: alexandru.elisei@arm.com, linux-kernel@vger.kernel.org, mark.rutland@arm.com, maz@kernel.org Subject: [PATCH v2 0/5] arm64: irqchip/gic-v3: Use compiletime constant PMR values Date: Mon, 17 Jun 2024 12:18:36 +0100 Message-Id: <20240617111841.2529370-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240617_041847_623436_39C299CF X-CRM114-Status: GOOD ( 19.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series optimizes the way regular IRQs are masked/unmasked when GICv3 pseudo-NMIs are used, removing the need for a static key in fast paths by using a priority value chosen dynamically at boot time. Thomas, would you be happy for this series to go through the arm64 tree? The key part of the series is the final patch which changes both arm64 and irqchip, and I expect merge conflicts or functional fallout to be contained to arm64. The GIC distributor and PMR/RPR can present different views of the interrupt priority space dependent upon the values of GICD_CTLR.DS and SCR_EL3.FIQ. Currently we treat the distributor's view of the priority space as canonical, and when the two differ we change the way we handle values in the PMR/RPR, using the `gic_nonsecure_priorities` static key to decide what to do. This approach works, but it's sub-optimal. When using pseudo-NMI we manipulate the distributor rarely, and we manipulate the PMR/RPR registers very frequently in code spread out throughout the kernel (e.g. local_irq_{save,restore}()). It would be nicer if we could use fixed values for the PMR/RPR, and dynamically choose the values programmed into the distributor. This series reworks the GIC code and arm64 architecture code to allow the use of compiletime-constant PMR values. This simplifies the logic for PMR management, and when using pseudo-NMI this results in smaller and better generated code for saving/restoring the irqflags, saving ~4K of text for defconfig + CONFIG_PSEUDO_NMI=y. The first patch add a new REPEAT_BYTE_U32() helper which can be useful for drivers. The second is a preparatory cleanup which I think makes sense regardless of the rest of the series. The third and fourth patches rework the GICv3 code to be able to choose priorities at boot time, and the final patch makes the actual switch. I've given this some light testing atop v6.10-rc1 with pseudo-NMI enabled (with priority debugging), along with lockdep on the following systems: * M1SDP Morello board, bare metal Where GICD_CTRL.DS=0, SCR_EL3.FIQ=0 Using shifted (NS) values in the distributor * M1SDP Morello board, KVM guest Where GICD_CTRL.DS=1, SCR_EL3.FIQ=0 Using unshifted values in the distributor * ThunderX2, KVM guest Where GICD_CTRL.DS=1, SCR_EL3.FIQ=0 Using unshifted values in the distributor On ThunderX2 bare-metal there is an existing boot-time hang when using pseudo-NMI which is not solved by this series. With this series applied, the logging added in patch 3 reports that GICD_CTRL.DS=1, SCR_EL3.FIQ=0, and so this should be using the same priorities which are seem to work in a guest. Since v1 [1]: * Add REPEAT_BYTE_U32() * Add MarcZ's Reviewed-by & Tested-by tags * Cleanup commit titles * Fix typos [1] https://lore.kernel.org/linux-arm-kernel/20240529172116.1313498-1-mark.rutland@arm.com/ Mark. Mark Rutland (5): wordpart.h: Add REPEAT_BYTE_U32() irqchip/gic-common: Remove sync_access callback irqchip/gic-v3: Make distributor priorities variables irqchip/gic-v3: Detect GICD_CTRL.DS and SCR_EL3.FIQ earlier arm64: irqchip/gic-v3: Select priorities at boot time arch/arm64/include/asm/arch_gicv3.h | 15 -- arch/arm64/include/asm/ptrace.h | 35 +--- arch/arm64/kernel/image-vars.h | 5 - drivers/irqchip/irq-gic-common.c | 22 +-- drivers/irqchip/irq-gic-common.h | 7 +- drivers/irqchip/irq-gic-v3-its.c | 11 +- drivers/irqchip/irq-gic-v3.c | 225 ++++++++++++------------ drivers/irqchip/irq-gic.c | 10 +- drivers/irqchip/irq-hip04.c | 6 +- include/linux/irqchip/arm-gic-common.h | 4 - include/linux/irqchip/arm-gic-v3-prio.h | 52 ++++++ include/linux/irqchip/arm-gic-v3.h | 2 +- include/linux/wordpart.h | 8 + 13 files changed, 201 insertions(+), 201 deletions(-) create mode 100644 include/linux/irqchip/arm-gic-v3-prio.h