From patchwork Wed Jun 26 22:32:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13713490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0178FC27C4F for ; Wed, 26 Jun 2024 22:33:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To: Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=XEVuTQCPlXzA0N7vJi65RCiA/S+prWj1TSr+w08eSzo=; b=W8dyrvWtuctLIk myh2k13StEA4uwSLIdoVUA3tf0aNgG9ki8f85PvkUaL3HTsb1KL0R8G1WbIGchQzMQegYczkfK/gv 7B+1/RPMZnX8mVfNUBMfI6cpz7MAfNtwWjgEOCYQmtfP8xAp+2Ax2a1CKCHnaVi2k/1opfgMQWLfM p8vrwaykY7OhkJWO68QsfTm+nb7Dxl+mNDpgurL7A2qpcv9bHxEwq+8rjrrEQtGlgfoJIfg0iLVs3 XIscgXamY6n8Q0nH7rhu3i0QZsU+XSt+ZIDf/Rd1dDvLQUVcy2AehiRuqtrs2wqqggb26wGweVrQJ imAlJyBWE2sV1xxe1s4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMbC7-00000008VVM-1U6y; Wed, 26 Jun 2024 22:32:51 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMbBw-00000008VNm-1b7Y for linux-arm-kernel@lists.infradead.org; Wed, 26 Jun 2024 22:32:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id BAC79CE2CA7; Wed, 26 Jun 2024 22:32:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C10BFC116B1; Wed, 26 Jun 2024 22:32:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719441157; bh=kk9N8S/9pjJldXV6CMVRpAD3Z0nGrY99ofJV3fvXtDg=; h=From:Subject:Date:To:Cc:From; b=LenWavY3RR1u7fsla77j3LoWys7mobMCJ868xPwsHHjVhhrGa2zkR8FfKufAQNyKW 8Halrva5mTGE0v3uBo3PXs0ytVoM3tJaJ9nzH07p+MGQUuHminXLoJ3nMecRe9P1tq Z5RQ6jskfaq08g133uVl2FlVocD8raPacTpI3CZR5AfoA7i61foKrpSGRVE2SswBnf ltRutt1pcygewz0dduJXRGFRj8ZyZhH8gnGnbnU/L7+X3/qO5C2Xl1NAU6YxJjz7Om w2TuGRS556hg2TtDOLNRj4+3oEssYXiSDCBT9Zz1X8jx3DtZvoLYfFfD3tnJUrocot /ag5Jm/ExjRFA== From: "Rob Herring (Arm)" Subject: [PATCH v2 00/12] arm64: Add support for Armv9.4 PMU fixed instruction counter Date: Wed, 26 Jun 2024 16:32:24 -0600 Message-Id: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAPiWfGYC/32NQQ6CQAxFr0K6tqYMKMrKexgWMFOgUQbSQaIh3 N2RA7h8L/nvrxBYhQOUyQrKiwQZfQRzSMD2te8YxUUGQyanMxVY64DT8MIMryjWz4qUZ8XJOUd 0MRB3k3Ir7715ryL3EuZRP/vFkv7sv9qSIqEtGmec5bbNmtuD1fPzOGoH1bZtX5matbyzAAAA To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240626_153240_814239_CAB70B4D X-CRM114-Status: GOOD ( 16.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the optional fixed instruction counter added in Armv9.4 PMU. Most of the series is a refactoring to remove the index to counter number conversion which dates back to the Armv7 PMU driver. Removing it is necessary in order to support more than 32 counters without a bunch of conditional code further complicating the conversion. Patches 1-2 are a fix and cleanup for the threshold support. Patch 1 is a dependency of patch 12. Patches 3-4 move the 32-bit Arm PMU drivers into drivers/perf/ and drop non-DT probe support. These can be taken first if there's no comments on them. Patch 5 is new to v2 and implements the common pattern of the linux/ header including the asm/ header of the same name. Patch 6 changes struct arm_pmu.num_events to a bitmap of events, and updates all the users. This removes the index to counter conversion on the PMUv3 and Armv7 drivers. Patch 7 updates various register accessors to use 64-bit values matching the register size. Patches 8-9 update KVM PMU register accesses to use shared accessors from asm/arm_pmuv3.h. Patches 10-11 rework KVM and perf PMU defines for counter indexes and number of counters. Patch 12 finally adds support for the fixed instruction counter. I tested this on FVP with VHE host and a guest. I tested the Armv7 PMU changes with QEMU. Signed-off-by: Rob Herring (Arm) --- Changes in v2: - Include threshold fix patches and account for threshold support in counter assignment. - Add patch including asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h - Fix compile error for Apple PMU - Minor review comments detailed in individual patches - Link to v1: https://lore.kernel.org/r/20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org --- Rob Herring (Arm) (12): perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold perf: arm_pmuv3: Drop unnecessary IS_ENABLED(CONFIG_ARM64) check perf/arm: Move 32-bit PMU drivers to drivers/perf/ perf: arm_v6/7_pmu: Drop non-DT probe support perf: arm_pmuv3: Include asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h perf: arm_pmu: Remove event index to counter remapping perf: arm_pmuv3: Prepare for more than 32 counters KVM: arm64: pmu: Use arm_pmuv3.h register accessors KVM: arm64: pmu: Use generated define for PMSELR_EL0.SEL access arm64: perf/kvm: Use a common PMU cycle counter define KVM: arm64: Refine PMU defines for number of counters perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter arch/arm/include/asm/arm_pmuv3.h | 20 +++ arch/arm/kernel/Makefile | 2 - arch/arm64/include/asm/arm_pmuv3.h | 55 +++++++- arch/arm64/include/asm/kvm_host.h | 8 +- arch/arm64/include/asm/sysreg.h | 1 - arch/arm64/kvm/pmu-emul.c | 15 +- arch/arm64/kvm/pmu.c | 87 +++--------- arch/arm64/kvm/sys_regs.c | 11 +- arch/arm64/tools/sysreg | 30 ++++ drivers/perf/Kconfig | 12 ++ drivers/perf/Makefile | 3 + drivers/perf/apple_m1_cpu_pmu.c | 4 +- drivers/perf/arm_pmu.c | 11 +- drivers/perf/arm_pmuv3.c | 154 +++++++++++---------- .../perf_event_v6.c => drivers/perf/arm_v6_pmu.c | 26 +--- .../perf_event_v7.c => drivers/perf/arm_v7_pmu.c | 90 ++++-------- .../perf/arm_xscale_pmu.c | 15 +- include/kvm/arm_pmu.h | 8 +- include/linux/perf/arm_pmu.h | 10 +- include/linux/perf/arm_pmuv3.h | 11 +- 20 files changed, 301 insertions(+), 272 deletions(-) --- base-commit: 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0 change-id: 20240607-arm-pmu-3-9-icntr-04375ddd0082 Best regards,