From patchwork Sun Jul 21 20:21:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 13738093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2B85C3DA5D for ; Sun, 21 Jul 2024 20:22:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=U5eklS5cz45wMWJaR+R7gbMjng5LM0/qSRkdL92OoGo=; b=z6UvG+pZ1MBp/Jsfu+hODsgTHu Ek3mm0AAH/wOx9fpMfkxSG5sKUkArLgkngea0lP+yVKEy5Dd0Xa9Yn0c8NLRV84VyGWdNqvwjXcGU 6cG7UKB8sdwNidAOVqxQRlYpSVXTcWZzedYUh4pN2EtkwMMTOSvEiww8wWuquyYS+kiW3yrkaXXf3 5Bvak6pahUTWZK3XAKq9cDHbLJEOhifpyACmrJ6/Pav4aXmNcy1zkPI+n2fr0LF756H+xeMrQBsF4 AeiN35Fo33GtRjbzN/YteV8ZYULHrV7uIIokth1W6wI24CEuJubAJZhTi2w+mSTmihbVU8MepbAVy XmqvsZ+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sVd49-00000007Ukw-16fD; Sun, 21 Jul 2024 20:21:57 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sVd3l-00000007UeS-3xJi for linux-arm-kernel@lists.infradead.org; Sun, 21 Jul 2024 20:21:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 556EAFEC; Sun, 21 Jul 2024 13:21:55 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 575443F73F; Sun, 21 Jul 2024 13:21:27 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , James Clark , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Jiri Olsa , Mark Rutland , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan Subject: [PATCH v1 0/6] perf auxtrace: Support multiple AUX events Date: Sun, 21 Jul 2024 21:21:07 +0100 Message-Id: <20240721202113.380750-1-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240721_132134_049664_E921487D X-CRM114-Status: GOOD ( 17.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is to support multiple events with the *same* type in Perf AUX trace. As the first enabled instance, the patch series enables multiple Arm SPE events (e.g. arm_spe_0, arm_spe_1, etc) in AUX trace. The solution for support multiple AUX events with same type is not difficult. As the events are same type, the trace data shares the same format and can be decoded by the same decoder. Essentially, this patch series is to extend the AUX trace flow from support single PMU event to multiple events. Note, this series does not support a more complex case - different types of AUX events, (e.g. Arm CoreSight event and Arm SPE events are enabled simultaneously). Patch 01 is a minor refactoring for dereference PMU pointer from evsel structure. Patches 02, 03 and 04 are to use the 'auxtrace' flag for support multiple AUX events. Firstly, we need to set the 'auxtrace' flag for Arm and s390 AUX events (Intel PT and bts have set already it). Afterwards, by using the evsel__is_aux_event() function, the core layer iterates the whole evlist - which allows the buffer index can be matched to corresponding AUX event. Patches 05 and 06 are to configure multiple SPE event in architecture dependent code. The old code is only initialize the first AUX event. with this series, it initializes all SPE PMU events. This patch series has been tested with the normal 'perf record' command and 'perf mem record' command. And verified for the decoding commands 'perf script' and 'perf mem report'. I observed one prominent issue is for per-CPU profiling. For example, when specifying option '-C 2' for profiling on CPU2, in this case the 'arm_spe_0' event supports CPU2 but the 'arm_spe_1' event does not support the CPU. As a result, 'arm_spe_1' event reports failure. This is likely a common issue for support Per-CPU profiling with multiple PMU events and every PMU event only support partial CPUs. This issue will be addressed later. Leo Yan (6): perf pmu: Directly use evsel's PMU pointer perf auxtrace arm: Set the 'auxtrace' flag for AUX events perf auxtrace s390: Set the 'auxtrace' flag for AUX events perf auxtrace: Iterate all AUX events when finish reading perf arm-spe: Extract evsel setting up perf arm-spe: Support multiple Arm SPE events tools/perf/arch/arm/util/pmu.c | 3 + tools/perf/arch/arm64/util/arm-spe.c | 107 ++++++++++++++++----------- tools/perf/arch/s390/util/auxtrace.c | 1 + tools/perf/util/auxtrace.c | 15 +++- tools/perf/util/pmu.c | 2 +- 5 files changed, 78 insertions(+), 50 deletions(-)