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Wed, 25 Sep 2024 10:43:51 GMT Received: from jingyw-gv.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Sep 2024 03:43:47 -0700 From: Jingyi Wang Subject: [PATCH v2 0/4] Add initial support for QCS8300 SoC and QCS8300 RIDE board Date: Wed, 25 Sep 2024 18:43:31 +0800 Message-ID: <20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAFTp82YC/22NQQ6CMBBFr0Jmbc20FBVX3sMQ0rSDTKIttEg0h LtbiUuX7yX//QUSRaYE52KBSDMnDj6D2hVge+NvJNhlBoVKY60qMdp0KhFb9jyxubduSizIHKT uSFellpCnQ6SOX1v22mTuOU0hvreXWX7tL4j6f3CWAoVDMrXpnEU8XsYnW/Z2b8MDmnVdP8rxR xi6AAAA To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: , , , , , , , Jingyi Wang , "Zhenhua Huang" , Xin Liu , "Kyle Deng" , Tingguo Cheng , Raviteja Laggyshetty X-Mailer: b4 0.15-dev-99b12 X-Developer-Signature: v=1; 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Features added and enabled: - CPUs with PSCI idle states - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect - QuP with uart - SMMU - QFPROM - Rpmhpd power controller - UFS - Inter-Processor Communication Controller - SRAM - Remoteprocs including ADSP,CDSP and GPDSP - BWMONs binding dependencies: - remoteproc: https://lore.kernel.org/linux-arm-msm/20240925-qcs8300_remoteproc_binding-v3-1-21b0c52b142b@quicinc.com/ - ufs-phy: https://lore.kernel.org/linux-arm-msm/20240925-qcs8300_ufs_phy_binding-v3-1-c1eb5c393b09@quicinc.com/ - ufs-controller: https://lore.kernel.org/all/20240911-qcs8300_ufs_binding-v2-1-68bb66d48730@quicinc.com/ - Reviewed - smmu: https://lore.kernel.org/all/20240911-qcs8300_smmu_binding-v2-1-f53dd9c047ba@quicinc.com/ - Applied - ipcc: https://lore.kernel.org/all/20240911-qcs8300_ipcc_binding-v2-1-ca15326c5d0f@quicinc.com/ - Applied - qfprom: https://lore.kernel.org/all/20240911-qcs8300_qfprom_binding-v2-1-d39226887493@quicinc.com/ - Reviewed - tcsr: https://lore.kernel.org/all/20240911-qcs8300_tcsr_binding-v2-1-66eb5336b8d1@quicinc.com/ - Reviewed - rmphpd: https://lore.kernel.org/all/20240920-add_qcs8300_powerdomains_driver_support-v1-1-96a2a08841da@quicinc.com/ - Reviewed - bwmon: https://lore.kernel.org/all/20240925-qcs8300_bwmon_binding-v1-1-a7bfd94b2854@quicinc.com/ - Reviewed - others: https://lore.kernel.org/all/20240911-qcs8300_binding-v2-0-de8641b3eaa1@quicinc.com/ - Reviewed build dependencies: - tlmm: https://lore.kernel.org/linux-arm-msm/20240819064933.1778204-1-quic_jingyw@quicinc.com/ - gcc: https://lore.kernel.org/all/20240822-qcs8300-gcc-v2-0-b310dfa70ad8@quicinc.com/ - interconnect: https://lore.kernel.org/linux-arm-msm/20240910101013.3020-1-quic_rlaggysh@quicinc.com/ patch made the following verifications: - Successfully ran dt_binding_check for binding files - Successfully ran dtbs_check with W=1 for dts - Features found on the SoC function verified. Signed-off-by: Jingyi Wang --- Changes in v2: - decoupled from the original series - Drop compatible for QCS8275 - fix property order and add line breaks - move sleep_clk node to qcs8300-ride.dts - move l3-cache nodes out of l2-cache nodes and remove cluster1/cluster2 - add BWMON nodes - commit-msg update - Link to v1: https://lore.kernel.org/r/20240904-qcs8300_initial_dtsi-v1-0-d0ea9afdc007@quicinc.com --- Jingyi Wang (4): dt-bindings: arm: qcom: document QCS8300 SoC and reference board arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS8300 arm64: dts: qcom: add initial support for QCS8300 DTSI arm64: dts: qcom: add base QCS8300 RIDE dts Documentation/devicetree/bindings/arm/qcom.yaml | 6 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 267 +++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 1375 +++++++++++++++++++++++ arch/arm64/configs/defconfig | 3 + 5 files changed, 1652 insertions(+) --- base-commit: 4d0326b60bb753627437fff0f76bf1525bcda422 change-id: 20240925-qcs8300_initial_dtsi-ea614fe45341 Best regards,