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Mon, 14 Oct 2024 06:55:24 -0700 (PDT) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2fb438c06f7sm8039641fa.55.2024.10.14.06.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2024 06:55:23 -0700 (PDT) From: Dmitry Baryshkov Subject: [PATCH v2 0/2] ARM: implement cacheinfo support (for v7/v7m) Date: Mon, 14 Oct 2024 16:55:19 +0300 Message-Id: <20241014-armv7-cacheinfo-v2-0-38ab76d2b7fa@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAMciDWcC/3WNwQrCMBBEf6Xs2UiTtNR48j+khzXdtguayEaCU vLvxt6FubyBebNBImFKcG42EMqcOIYK5tCAXzEspHiqDKY1VtcolEcelEe/Eoc5Kjdjby2SHTR BXT2FZn7vxutYeeX0ivLZD7L+tf9dWatWOTpNXdfeeje5y50DSjxGWWAspXwBEFUdC68AAAA= To: Sudeep Holla , Ard Biesheuvel , Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Arnd Bergmann X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1720; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=NGIUHcjVkpQKPY7o+OZAEBnz+K2Zb66rg/sEoqDDM+w=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnDSLKspHgnnvhllB+AgI0EeCIaGlxtXGxNHkON nC6OmULEyyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZw0iygAKCRCLPIo+Aiko 1V5tB/9rmFlo9KKXviiA6KgOmxsQhasXCsCn1VGx/8lSrsc1PrMyKiKYmqAYlUhs8LMcfD10A28 U7ZAaxxdCoa5cWf1AFdV1HGX/GsDqE6EFa08ZjgTejapXDUaItpgZnPe8P+lytEI9W7nUR+aFxm gA5xSTaT5mDFkz7ec+1JRoybiXUMZOHyMgeChqyjDt0GaRj74TQltoN1/MrY98TqtqWIiDCTdBq H+5lpUlRsHl6YDzMxcpnknQUoLLp/ohl2bRWmnLTz8su9JbBgDlPr++Qb7kwbP8Ji3P3fXx0qUG AfL3XC5vS+W5B+0elGBFa2+etDDYKJuU/QBkOOU0JkfPo63/ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241014_065527_610330_C5CEB6FA X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Follow the ARM64 platform and implement simple cache information driver. As it reads data from CTR (ARMv6+) and CLIDR (ARMv7+) registers, it is limited to the ARMv7 / ARMv7M, providing simple fallback or just returning -EOPNOTSUPP in case of older platforms. In theory we should be able to skip CLIDR reading and assume that Dcache and Icache (or unified L1 cache) always exist if CTR is supported and returns sensible value. However I think this better be handled by the maintainers of corresponding platforms. Other than just providing information to the userspace, this patchset is required in order to implement L2 cache driver (and in the end CPU frequency scaling) on ARMv7-based Qualcomm devices. Signed-off-by: Dmitry Baryshkov --- Changes in v2: - Handle cores like ARM1176, which have cpu_architecture() == CPU_ARCH_ARMv7 (because of VMSAv7 implementation), but no CLIDR register (because they are ARMv6) (Arnd). - Link to v1: https://lore.kernel.org/r/20231231-armv7-cacheinfo-v1-0-9e8d440b59d9@linaro.org --- Dmitry Baryshkov (2): ARM: add CLIDR accessor functions ARM: implement cacheinfo support arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/include/asm/cachetype.h | 13 +++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 173 +++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 6 files changed, 195 insertions(+), 1 deletion(-) --- base-commit: 7f773fd61baa9b136faa5c4e6555aa64c758d07c change-id: 20231231-armv7-cacheinfo-9fa533ae371e Best regards,