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Wed, 16 Oct 2024 14:40:19 +0200 From: Amelie Delaunay Subject: [PATCH v3 0/9] STM32 DMA3 updates for STM32MP25 Date: Wed, 16 Oct 2024 14:39:52 +0200 Message-ID: <20241016-dma3-mp25-updates-v3-0-8311fe6f228d@foss.st.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIABi0D2cC/23OSwqDMBCA4atI1o3k0UTrqvcoXUQzqVloJGNDi 3j3RqHQgst/YL6ZhSBED0iaYiERkkcfxhzyVJCuN+MDqLe5iWDizBlX1A5G0mESij4na2ZAais ndKVky6wleW+K4PxrN2/33L3HOcT3fiLxbfrV2IGWOGXUWMe0lJeag7m6gFjiXHZhIJuXxK9x9 FES2Wi1BMGV0tDV/8a6rh/Ppn3H+AAAAA== X-Change-ID: 20241015-dma3-mp25-updates-d7f26753b0dd To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Amelie Delaunay X-Mailer: b4 0.14.2 X-Originating-IP: [10.252.17.239] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_134300_263727_D79536E2 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The HW version of STM32 DMA3 inside STM32MP25 requires some tunings to meet the needs of the interconnect. This series adds the linked list refactoring feature to have optimal performance when addressing the memory, and it adds the use of two new bits in the third cell specifying the DMA transfer requirements: - bit[16] to prevent packing/unpacking mode to avoid bytes loss in case of interrupting an ongoing transfer (e.g. UART RX), - bit[17] to prevent linked-list refactoring because some peripherals (e.g. FMC ECC) require a one-shot transfer, they trigger the DMA only once. It also adds platform data to clamp the burst length on AXI port, especially when it is interconnected to AXI3 bus, such as on STM32MP25. Finally this series also contains STM32MP25 device tree updates, to add DMA support on SPI, I2C, UART and apply the tunings introduced. Signed-off-by: Amelie Delaunay --- Changes in v3: - Refine commit description of patch 4 about preventing additionnal transfers, as per Rob's suggestion. - Link to v2: https://lore.kernel.org/r/20241015-dma3-mp25-updates-v2-0-b63e21556ec8@foss.st.com Changes in v2: - Reword commit title/message/content of patch 4 about preventing additionnal transfers, as per Rob's suggestion - Rework AXI maximum burst length management using SoC specific compatible, as pointed out by Rob - Drop former patches 6 and 8, which are no longer relevant - Link to v1: https://lore.kernel.org/r/20241010-dma3-mp25-updates-v1-0-adf0633981ea@foss.st.com --- Amelie Delaunay (9): dt-bindings: dma: stm32-dma3: prevent packing/unpacking mode dmaengine: stm32-dma3: prevent pack/unpack thanks to DT configuration dmaengine: stm32-dma3: refactor HW linked-list to optimize memory accesses dt-bindings: dma: stm32-dma3: prevent additional transfers dmaengine: stm32-dma3: prevent LL refactoring thanks to DT configuration dmaengine: stm32-dma3: clamp AXI burst using match data arm64: dts: st: add DMA support on U(S)ART instances of stm32mp25 arm64: dts: st: add DMA support on I2C instances of stm32mp25 arm64: dts: st: add DMA support on SPI instances of stm32mp25 .../bindings/dma/stm32/st,stm32-dma3.yaml | 6 ++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 75 +++++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 2 + drivers/dma/stm32/stm32-dma3.c | 119 +++++++++++++++++---- 4 files changed, 182 insertions(+), 20 deletions(-) --- base-commit: 76355c25e4f71ee4667ebaadd9faf8ec29d18f23 change-id: 20241015-dma3-mp25-updates-d7f26753b0dd Best regards,