From patchwork Wed Oct 16 23:30:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13839063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98ECBD2F7D6 for ; Wed, 16 Oct 2024 23:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=NTFzU59PBYtGMvWw4oj+dZrXWgp3ksm4qtF5B8NQwOo=; b=o/jkDw8pIIXlUcm6zo9U0cVctY 1noAC/Rvz6rAxXZN9KbbVoKm9/RgLDNOLDk+PEQhG5e0HBbFtFrvGxj5sL/5dKg4c6ZD0xxpaLN6s +h0Xpz3Iy9DHddV/94hQnjckwd0eE+YnTqn8uScX/w+KGhJJb1ePK/XkiC14wr27A7m7dI7FFew8/ FGeVzSITm2ua5ulfm3xbWG1FjLyZ9HYWx1Ft3mYB340QBPqG/edl7oap+rkSZw7ER91AxFD6vv1e0 1/4n4Tkm7w1Y9ggTtJdS3oveJIowLznp5bg3kn3NEQsIxDyYIptmQkWYsdWRAi5lD90iYBAIZPElP I8M5QQSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1t1DZO-0000000DEq7-2rUx; Wed, 16 Oct 2024 23:36:46 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1t1DTj-0000000DEDF-3Tj1 for linux-arm-kernel@lists.infradead.org; Wed, 16 Oct 2024 23:30:57 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUk5A053745; Wed, 16 Oct 2024 18:30:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729121446; bh=NTFzU59PBYtGMvWw4oj+dZrXWgp3ksm4qtF5B8NQwOo=; h=From:To:CC:Subject:Date; b=cuNhSdBUHkFxWysqKv3x3StWLrhRePWD+PB9BZX03U8DvyOvGO6gC2MyGIQ8vOjUM tVxYWADY7xJkrkwYZi9sFoNfsXKc/vV7SgKrDMCN3NBHGDkWqpoEJUOx9wI3R0I7a2 C5wJPHCAOinNq1hI53r/O2MfoYTf6M6j3hgBzDxA= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 49GNUk9K014824 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 16 Oct 2024 18:30:46 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 16 Oct 2024 18:30:45 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 16 Oct 2024 18:30:45 -0500 Received: from fllvsmtp7.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49GNUj7h070988; Wed, 16 Oct 2024 18:30:45 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 0/5] Use ti,j784s4-pcie-ctrl for PCIe CTRL spaces Date: Wed, 16 Oct 2024 18:30:39 -0500 Message-ID: <20241016233044.240699-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241016_163055_934266_66B30004 X-CRM114-Status: UNSURE ( 8.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello all, Now that we have ti,j784s4-pcie-ctrl[0] let's use it. This makes these K3 SoCs all match what is already done for J784s4. No functional change, DT changes are fully backwards and forwards compatible. Thanks, Andrew [0] commit cc1965b02d6c ("dt-bindings: mfd: syscon: Add ti,j784s4-pcie-ctrl compatible") Andrew Davis (5): dt-bindings: soc: ti: ti,j721e-system-controller: Add PCIe ctrl property arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region arm64: dts: ti: k3-j721s2: Add PCIe ctrl node to scm_conf region arm64: dts: ti: k3-am64: Add PCIe ctrl node to main_conf region .../soc/ti/ti,j721e-system-controller.yaml | 5 ++++ arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++- .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++--- .../boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++- 7 files changed, 49 insertions(+), 9 deletions(-)