| Message ID | 20250217061142.38480-5-ziyao@disroot.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | Support clock and reset unit of Rockchip RK3528 | expand |
On Mon, 17 Feb 2025 06:11:41 +0000, Yao Zi wrote: > Similar to previous Rockchip SoCs, reset controller on RK3528 shares > MMIO region with clock controller, combined as CRU. They're represented > as a single node in dt. > > For the reset controller, only bindings are included in this series > because it's hard to test the reset controller without support for some > peripherals (e.g. pinctrl). I'd like to first make dt and basic > peripherals available, then submit the driver. > > [...] Applied, thanks! [1/5] dt-bindings: clock: Document clock and reset unit of RK3528 commit: e0c0a97bc308f71b0934e3637ac545ce65195df0 [2/5] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE commit: 651aabc9fb0f354ad2ba5fd06a6011e652447489 [3/5] clk: rockchip: Add clock controller driver for RK3528 SoC commit: 5d0eb375e6857d270f6376d161ef02a1b7183fa2 [4/5] arm64: dts: rockchip: Add clock generators for RK3528 SoC commit: 858cdcdd11cf9913756297d3869e4de0f01329ea [5/5] arm64: dts: rockchip: Add UART clocks for RK3528 SoC commit: b9454434d0349223418f74fbfa7b902104da9bc5 Best regards,
Similar to previous Rockchip SoCs, reset controller on RK3528 shares MMIO region with clock controller, combined as CRU. They're represented as a single node in dt. For the reset controller, only bindings are included in this series because it's hard to test the reset controller without support for some peripherals (e.g. pinctrl). I'd like to first make dt and basic peripherals available, then submit the driver. This is tested on Radxa E20C board. With some out-of-tree drivers, I've successfully brouhgt up UART, pinctrl/gpio and I2C. A clock dump could be obtained from [1]. [1]: https://gist.github.com/ziyao233/032961d1eebeecb9a41fea2d690e8351 Changed from v2 - dt-bindings: - drop redundant assigned-clocks and assigned-clock-rates properties - improve description of input clock gmac0 - Link to v2: https://lore.kernel.org/all/20250108114605.1960-2-ziyao@disroot.org/ Changed from v1 - dt-bindings: - relicense binding headers as GPL-2.0-only OR MIT - use gapless integers starting from 0 for binding IDs - make input clocks essential, add corresponding description - rename the input clock that is generated by phy module as "gmac0" - style fixes - driver: - format in the common Rockchip driver style - drop initializing code of the reset controller, as it'll not be supported in this series - Link to v1: https://lore.kernel.org/linux-rockchip/20241001042401.31903-2-ziyao@disroot.org/ Yao Zi (5): dt-bindings: clock: Document clock and reset unit of RK3528 clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE clk: rockchip: Add clock controller driver for RK3528 SoC arm64: dts: rockchip: Add clock generators for RK3528 SoC arm64: dts: rockchip: Add UART clocks for RK3528 SoC .../bindings/clock/rockchip,rk3528-cru.yaml | 64 + arch/arm64/boot/dts/rockchip/rk3528.dtsi | 68 +- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-pll.c | 10 +- drivers/clk/rockchip/clk-rk3528.c | 1114 +++++++++++++++++ drivers/clk/rockchip/clk.h | 22 + .../dt-bindings/clock/rockchip,rk3528-cru.h | 453 +++++++ .../dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++ 9 files changed, 1975 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml create mode 100644 drivers/clk/rockchip/clk-rk3528.c create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h