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bh=W4Wi7swWBNgxc2OK1K68tHTCFCmIPvqaSqBPxwVVoF0=; b=Sv4Dncz7BZQzbc5X2reRGaJaLL2IPwXy7ajWXEXiDojWIHRJmZ6xchakDDaQYAooFo vQU+/pnVNVby4YnRnZ6O1J17zDQdmXgp1YSog+l20dI1O3XYgOWO3XlgQoW6+fyO1MvL Lv5ZaKZa6WMdSI9sJB6Iw7iYjeZHM0zENzgHHk/cQCg6JKUFhlH20X++GfutHTDBcfEe AndWoZX5ia+5BFLReotn8pIojF8rSx2uJobEpfqg1VWm92/6cwlFo7B56/n+hQt7b26+ MTSqVg75hRrQ/bHW/rIsjg74KCeOn4RQMj9MEt/zSmET5OagfPNsrkroTZZmwxFCqp9n GnwA== X-Gm-Message-State: AA+aEWa7Oh+QYmC3mKEM7AqOjjn0BtT7/ze0D90n6Nx8LhbweQ8qcsVM QyeZXNGuXsIUvJQZ1ptbW7I= X-Google-Smtp-Source: AFSGD/Xo2l8coJI3/3elUD+eZhwi+Me2yX3e2acv11avRxN4P6EgCQKuY5VGq37Q7S4WK78UAKbMEg== X-Received: by 2002:a1c:2e08:: with SMTP id u8mr4461750wmu.152.1543444451189; Wed, 28 Nov 2018 14:34:11 -0800 (PST) Received: from ThinkPad.home ([185.219.177.239]) by smtp.gmail.com with ESMTPSA id g198sm180244wmd.23.2018.11.28.14.34.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:34:10 -0800 (PST) From: Mesih Kilinc To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v5 00/17] initial support for "suniv" Allwinner new ARM9 SoC Date: Thu, 29 Nov 2018 01:33:10 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_143423_497377_74767373 X-CRM114-Status: GOOD ( 16.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mesih Kilinc , Julian Calaby , Linus Walleij , Daniel Lezcano , Russell King , Marc Zyngier , Chen-Yu Tsai , Rob Herring , Maxime Ripard , Icenowy Zheng MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This is the fifth version of patchset for Allwinner ARMv5 F1C100s SoC. Addressed comments from Maxime Ripard and Rob Herring, added signatures. Changes since v4: - Patch "dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl" - This patch applied for 4.21. - Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)" - This patch applied for 4.21. - Patch "dt-bindings: clock: Add Allwinner suniv F1C100s CCU" - Fixed license identifier position - Added DMA fields. - Patch "clk: sunxi-ng: add support for suniv F1C100s SoC" - Added DMA reset and clock support. - Patch "ARM: dts: suniv: add initial DTSI file for F1C100s" - Remove dt-binding headers. - Fix uart0 pin label. - Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano" - Fix uart0 pin label. Changes since v3: - Patch "ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs" - Remove CONFIG_ARCH_SUNXI_Vx. Use ARCH_MULTI_Vx to differentiate SoC's - Change KConfig ARCH_SUNXI selection: 'select' to 'default'. - Patch "irqchip/sun4i: Add a struct to hold global variables" - Split irq_sun4i.c changes to 3 patch. - Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)" - pinctrl-suniv-f1c100s: remove: disable_strict_mode = true - Patch "ARM: dts: suniv: add initial DTSI file for F1C100s" - suniv-f1c100s.dtsi: remove unnecessary componenets. - Instead of patching drivers, add original compatible string with f1c100s compatibles. - Add Acked-by signatures. Changes since v2: - Patch "ARM: sunxi: add Allwinner ARMv5 SoCs" - Move SUN4I_TIMER option to ARCH_SUNXI - Added help text for MACH_SUNIV - Patch "irqchip/sun4i: add support for suniv interrupt controller" - Defined sunxi_irq_chip_data struct and used it to differentiate registers between different chips. - Patch " ARM: dts: suniv: add initial DTSI file for F1C100s" - Removed unnecessary fake clock. - Fixed compatible strings. Changes since v1: - Patch "ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate ARMv5/v7 Allwinner SoCs" - Instead of using a common bool config use a common menuconfig. - Use ARCH_MULTI_V7 to differentiate V7 SoCs. - Addressed comment from Julian Calaby - Patch "ARM: sunxi: add Allwinner ARMv5 SoCs" - Use ARCH_MULTI_V5 to differentiate V5 SoCs. - removed "allwinner,suniv" board compatible string - Added dt-bindings - Patch "irqchip/sun4i: add support for suniv interrupt controller" - Added dt-bindings - Changed "allwinner,suniv-ic" to "allwinner,suniv-f1c100s-ic" - Patch "clocksource: sun4i: add a compatible for suniv" - Added dt-bindings - Changed "allwinner,suniv-timer" to "allwinner,suniv-f1c100s-timer" - Patch "pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs)" - Added dt-bindings - Renamed suniv-pinctrl to suniv-f1c100s-pinctrl - Patch "clk: sunxi-ng: add support for suniv F1C100s SoC" - Added dt-bindings - Renamed suniv-ccu to suniv-f1c100s-ccu - Patch "ARM: suniv: f1c100s: add device tree for Lichee Pi Nano" - Addressed comment from Rask Ingemann Lambertsen Thanks! Mesih Kilinc (17): ARM: Check ARCH_MULTI_V7 to differentiate ARMv5/v7 Allwinner SoCs dt-bindings: arm: Add new Allwinner ARMv5 F1C100s SoC ARM: sunxi: add Allwinner ARMv5 SoCs dt-bindings: interrupt-controller: Add suniv interrupt-controller irqchip/sun4i: Add a struct to hold global variables irqchip/sun4i: Move IC specific register offsets to struct irqchip/sun4i: Add support for Allwinner ARMv5 F1C100s dt-bindings: timer: Add Allwinner suniv timer clocksource: sun4i: add a compatible for suniv dt-bindings: pinctrl: Add Allwinner suniv F1C100s pinctrl pinctrl: sunxi: add support for suniv F1C100s (newer F-series SoCs) dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: sram: Add Allwinner suniv F1C100s dt-bindings: watchdog: Add Allwinner ARMv5 F1C100s wdt ARM: dts: suniv: add initial DTSI file for F1C100s ARM: suniv: f1c100s: add device tree for Lichee Pi Nano Documentation/devicetree/bindings/arm/sunxi.txt | 1 + .../devicetree/bindings/clock/sunxi-ccu.txt | 1 + .../interrupt-controller/allwinner,sun4i-ic.txt | 4 +- .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + .../devicetree/bindings/sram/sunxi-sram.txt | 4 + .../bindings/timer/allwinner,sun4i-timer.txt | 4 +- .../devicetree/bindings/watchdog/sunxi-wdt.txt | 1 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 + arch/arm/boot/dts/suniv-f1c100s.dtsi | 147 ++++++ arch/arm/mach-sunxi/Kconfig | 19 +- arch/arm/mach-sunxi/sunxi.c | 10 + drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 541 +++++++++++++++++++++ drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 34 ++ drivers/clocksource/sun4i_timer.c | 5 +- drivers/irqchip/irq-sun4i.c | 106 ++-- drivers/pinctrl/sunxi/Kconfig | 4 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 416 ++++++++++++++++ include/dt-bindings/clock/suniv-ccu-f1c100s.h | 70 +++ include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 ++ 23 files changed, 1408 insertions(+), 33 deletions(-) create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h