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Thu, 19 Nov 2020 15:56:15 -0800 (PST) Received: from localhost.localdomain ([188.24.159.61]) by smtp.gmail.com with ESMTPSA id i3sm452987ejh.80.2020.11.19.15.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 15:56:14 -0800 (PST) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Vinod Koul , Wolfram Sang , Ulf Hansson , Dan Williams Subject: [PATCH v2 00/18] Add CMU/RMU/DMA/MMC/I2C support for Actions Semi S500 SoCs Date: Fri, 20 Nov 2020 01:55:54 +0200 Message-Id: X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201119_185617_725556_3C7BE4E5 X-CRM114-Status: GOOD ( 17.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This patchset brings a series of improvements for the Actions Semi S500 SoCs family, by adding support for Clock & Reset Management Units, DMA, MMC, I2C & SIRQ controllers. Please note the patches consist mostly of DTS and bindings/compatibles changes, since all the work they depend on has been already merged, i.e. clock fixes/additions, pinctrl driver, sirq driver. For the moment, I have only enabled the features I could test on RoseapplePi SBC. Thanks, Cristi Changes in v2: - Added new bindings/compatibles for S500 DMA, MMC & I2C controllers - Added support for the SIRQ controller - Added new entries in MAINTAINERS - Updated naming of some patches in v1 Cristian Ciocaltea (18): arm: dts: owl-s500: Add Clock Management Unit arm: dts: owl-s500: Set CMU clocks for UARTs arm: dts: owl-s500: Add Reset controller dt-bindings: dma: owl: Add compatible string for Actions Semi S500 SoC dmaengine: owl: Add compatible for the Actions Semi S500 DMA controller arm: dts: owl-s500: Add DMA controller arm: dts: owl-s500: Add pinctrl & GPIO support dt-bindings: mmc: owl: Add compatible string for Actions Semi S500 SoC arm: dts: owl-s500: Add MMC support dt-bindings: i2c: owl: Convert Actions Semi Owl binding to a schema MAINTAINERS: Update entry for Actions Semi Owl I2C binding i2c: owl: Add compatible for the Actions Semi S500 I2C controller arm: dts: owl-s500: Add I2C support arm: dts: owl-s500: Add SIRQ controller arm: dts: owl-s500-roseapplepi: Use UART clock from CMU arm: dts: owl-s500-roseapplepi: Add uSD support arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configuration MAINTAINERS: Add linux-actions ML for Actions Semi Arch .../devicetree/bindings/dma/owl-dma.yaml | 5 +- .../devicetree/bindings/i2c/i2c-owl.txt | 29 ---- .../devicetree/bindings/i2c/i2c-owl.yaml | 62 ++++++++ .../devicetree/bindings/mmc/owl-mmc.yaml | 4 +- MAINTAINERS | 3 +- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 97 +++++++++++- arch/arm/boot/dts/owl-s500.dtsi | 140 ++++++++++++++++++ drivers/dma/owl-dma.c | 1 + drivers/i2c/busses/i2c-owl.c | 1 + 9 files changed, 304 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-owl.yaml