From patchwork Thu Dec 10 12:15:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 11964355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41086C4167B for ; Thu, 10 Dec 2020 12:17:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D7F5023B70 for ; Thu, 10 Dec 2020 12:17:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D7F5023B70 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=VD2LbQ5h9EopQF+4UZXX0ofFEeNyHgAN5sj7R98S1vA=; b=f17Bevn1B5UB9RXZ8d7P7LNMy5 F4RGqJQOu9hCJJp7Muh8qk8SaLpGRnpYb8Xbs1RyS6EetMPRVTnGWTd4QLg2k3Akhq6QOYGzz1ccW Se3w/vIVrqdIi5Yu3Y86XWMb9iECyglpm4Whwr868PA/K3GkGjCR9b+JWgVkcdg7BuH2h4A/S3Bf1 vLUYgiFAl2moeqolFOvLCmSzismPwOKw6JExr3J2jfNtGlsIl4pWxMp4zPWa24SCMs9Ll1gkClmQB IfidPwikurT+rFvxU9Bl+uSgUxRB9AODh/TsBUMNqR+pwZFW4XrSQPMFHBZ5s3DwwSvDn8FWucf2z MVWHp7Fw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1knKsB-0006KH-7V; Thu, 10 Dec 2020 12:16:39 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1knKs0-0006HJ-I5 for linux-arm-kernel@lists.infradead.org; Thu, 10 Dec 2020 12:16:29 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id 49959440048; Thu, 10 Dec 2020 14:16:08 +0200 (IST) From: Baruch Siach To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , Lee Jones , Linus Walleij , Bartosz Golaszewski , Rob Herring Subject: [PATCH v4 0/3] gpio: mvebu: Armada 8K/7K PWM support Date: Thu, 10 Dec 2020 14:15:57 +0200 Message-Id: X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201210_071628_917242_B9E309E1 X-CRM114-Status: GOOD ( 15.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Lunn , Baruch Siach , linux-pwm@vger.kernel.org, Gregory Clement , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Chris Packham , Thomas Petazzoni , Ralph Sennhauser , Sascha Hauer , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series makes two changes to v3: * Remove patches that are in LinusW linux-gpio for-next and fixes * Rename the 'pwm-offset' property to 'marvell,pwm-offset' as suggested by Rob Herring The original cover letter follows (with DT property name updated). The gpio-mvebu driver supports the PWM functionality of the GPIO block for earlier Armada variants like XP, 370 and 38x. This series extends support to newer Armada variants that use CP11x and AP80x, like Armada 8K and 7K. This series adds adds the 'marvell,pwm-offset' property to DT binding. 'marvell,pwm-offset' points to the base of A/B counter registers that determine the PWM period and duty cycle. The existing PWM DT binding reflects an arbitrary decision to allocate the A counter to the first GPIO block, and B counter to the other one. In attempt to provide better future flexibility, the new 'marvell,pwm-offset' property always points to the base address of both A/B counters. The driver code still allocates the counters in the same way, but this might change in the future with no change to the DT. Tested AP806 and CP110 (both) on Armada 8040 based system. Baruch Siach (3): gpio: mvebu: add pwm support for Armada 8K/7K arm64: dts: armada: add pwm offsets for ap/cp gpios dt-bindings: ap806: document marvell,gpio pwm-offset property .../arm/marvell/ap80x-system-controller.txt | 8 ++ arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 + arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++ drivers/gpio/gpio-mvebu.c | 101 ++++++++++++------ 4 files changed, 89 insertions(+), 33 deletions(-)