From patchwork Fri Jan 28 07:09:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Prakash Ranjan X-Patchwork-Id: 12728011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65DCDC433F5 for ; Fri, 28 Jan 2022 07:11:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=9AUdXDcxlwF99w6NYHuuf0vo9+nm0wSEdG4v35eHSEs=; b=NEF5F4yTFenc78 UpwDdeeEBWGmEBj0BJky+IDySD2p+dJHTtqQzAR6Efxm4QrFTF5lsK3329KfMS07BxhjnCyK5MoHe HWk1AlJI1jhfr0wjF/3hS/tQ9sl6ixTGzEN+rAifOLYoucm4ytLOnTobofRrdTLPEcHgfKGj0eE1z 5lXWDlFVmNKVxSGUd1Q4uoG+k5eQwp3LZxv4OrG0JWYqh4JIFJETBv3gL+S1/EeXR2eTdT1YFjInp JHHovo4CWqi3KOvHy71yN+4W83C4Xm9UdvBnGegsTwwAujDofhg0tYBz5P663+D9hMZA5ysp/Un17 rV0SemAfuKnhFjkjv3xA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDLOs-000jAs-KL; Fri, 28 Jan 2022 07:10:26 +0000 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nDLOg-000j71-Hj for linux-arm-kernel@lists.infradead.org; Fri, 28 Jan 2022 07:10:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1643353814; x=1674889814; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Jv4vpwDFKDd0TI5RGz7EkxlWKUVVnZnZU0bLRUkF/74=; b=TcW3qfkXaDF2ta50+UyDR4sbvw207eDC8X/xJc4LhJj6iNwVzuT9armg YcAQ6Rilll4EbB5MmrljXTG9kzAt2zw7BxUhcXyRyr1gz/j4XfhWmUjwK tz3E5dIrWWVZrvzJL4fjZGmQtnREFltXH7nH0AojsJ1+AK2754U5WA+tM g=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 27 Jan 2022 23:10:14 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jan 2022 23:10:02 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 27 Jan 2022 23:10:00 -0800 Received: from blr-ubuntu-253.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 27 Jan 2022 23:09:56 -0800 From: Sai Prakash Ranjan To: Andy Gross , Bjorn Andersson CC: , , , , Vinod Koul , Manivannan Sadhasivam , Rajendra Nayak , Sai Prakash Ranjan Subject: [PATCH 0/9] soc: qcom: llcc: Add LLCC support for SM8450 SoC Date: Fri, 28 Jan 2022 12:39:24 +0530 Message-ID: X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220127_231014_640893_B99D5A2A X-CRM114-Status: UNSURE ( 9.66 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch series adds support for LLCC on SM8450 SoC. It mainly consists of LLCC driver changes to incorporate newer LLCC HW found on SM8450 SoC and the corresponding DT bits to enable LLCC. Based on qcom/for-next branch. Huang Yiwei (1): soc: qcom: llcc: Add support for 16 ways of allocation Sai Prakash Ranjan (8): soc: qcom: llcc: Update the logic for version info extraction soc: qcom: llcc: Add write-cache cacheable support soc: qcom: llcc: Add missing llcc configuration data soc: qcom: llcc: Update register offsets for newer LLCC HW soc: qcom: llcc: Add configuration data for SM8450 SoC dt-bindings: arm: msm: Add LLCC compatible for SM8350 dt-bindings: arm: msm: Add LLCC compatible for SM8450 arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node .../bindings/arm/msm/qcom,llcc.yaml | 2 + arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 ++ drivers/soc/qcom/llcc-qcom.c | 102 +++++++++++++++--- include/linux/soc/qcom/llcc-qcom.h | 9 +- 4 files changed, 104 insertions(+), 16 deletions(-) base-commit: 073a39a2a63abd46339a50eb07bd23958d99efbe prerequisite-patch-id: 33fc8487573f4dd2ef21bfdfcf57d1437f456df3 prerequisite-patch-id: 026a0e76224498cec9ad15cbbc452f8f4fcdbca9 prerequisite-patch-id: 626323d13e5cc60434e225544b71314fd84adf90 prerequisite-patch-id: a1d79b7d366eb3a749621998580d8607a852a432 prerequisite-patch-id: 51d51021554581d9ccf510a8c9087748b9a77019 prerequisite-patch-id: ecbbd03ca61082e78754d52d1b3e99848185b4d1 prerequisite-patch-id: 6120d52065436b3d5fcc4aa509af2046bea1e344 prerequisite-patch-id: 388f5c230d39b7181a0f563b6fc5b3e35d4d7f75