From patchwork Sun Jun 12 10:18:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12878689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33A6DC433EF for ; Sun, 12 Jun 2022 10:20:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=43EOJK7HRo2/06NZ2xhdk+ZeQ2GpVkp8a7YWguIyyF4=; b=zmiICwO/N5qMd+ F7zrxYHRTYYAd1XVJrb4lt04Rhjg/juPM+vecTK8VNqtfTo+ugbZk5a8VYmwwMnzCIJ45lOdI8BOv fAAjnVwFQX1W5nMQ5+2w+I9InfJwlLohXKVfGpxcQnPp+Ksc3oUXGWC5G79pVmrjKgrir36pxyVaG a8hEzNPzy5FSlcu3840+beL4pByrk5ePuf6iQ+Z7vnPrvuEHDzVvVcVSk4H9LXd4eTHJjsH8xqTGx qWIiYN5OvC8jBd9tx9TLqQ+SDmUyYrfkhcd725toDGEYESRGcsV7CGLLZuOwAhR/PXXb/lCWzxd3m Ai6ezhwILsgM6gCRHpLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0Kgg-00GDhI-OP; Sun, 12 Jun 2022 10:19:18 +0000 Received: from wiki.tkos.co.il ([84.110.109.230] helo=mail.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o0KgM-00GDcJ-3f for linux-arm-kernel@lists.infradead.org; Sun, 12 Jun 2022 10:19:00 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id 29882440871; Sun, 12 Jun 2022 13:18:32 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1655029112; bh=F94aNh3JlGBDRxuX6bcvrpui+k0ajuhAbaAtoXHdaz4=; h=From:To:Cc:Subject:Date:From; b=PstxhpQ2j2zL3XgaOwUiUHxsE9eAiuy2IiU7fBvREIvKdgvqEgd5dXEF41ZxmDlHV +h55M7mxikZ017Rgx9sTFXJVK+smeZdCsxB2KH2fZ4qv58XwhqeZHFU+hz7+q4+tr/ iHaod/SMzKZm4GnP+px3pl3XQHEauQPgwzkhSdf+nuF2PGz3ZaYeqgWxVx/Gl0nr0P G2lMZI8ILiENAe/aHZ+Ii1/P56l1VU3+8txwbvLUn4iX1esyCcs1dz0ok4VJuwbZ6F EGwuaxAF2158bHUG3p1ihGFjn7e75S2J3mgEGa4L5BzN6BmJqRUOpyk/6bNVuPmoJ7 MVsh0zVsvEezA== From: Baruch Siach To: Andy Gross , Bjorn Andersson , Stanimir Varbanov Cc: Baruch Siach , Kathiravan T , Selvam Sathappan Periakaruppan , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , =?utf-8?q?Pali_Roh=C3=A1r?= , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH v7 0/3] PCI: IPQ6018 platform support Date: Sun, 12 Jun 2022 13:18:32 +0300 Message-Id: X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220612_031858_393049_97903958 X-CRM114-Status: GOOD ( 13.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v7: * Use FIELD_PREP for power limit and scale fields * Add Stanimir Varbanov to Cc * Rebase on v5.19-rc1 Changes in v6: * Drop DT patch applied to the qcom tree * Normalize driver changes subject line * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros * Drop a vague comment about ASPM configuration * Add a comment about the source of delay periods Changes in v5: * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) Changes in v4: * Drop applied DT bits * Add max-link-speed that was missing from the applied v2 patch * Rebase the driver on v5.16-rc3 Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (2): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Selvam Sathappan Periakaruppan (1): PCI: qcom: Add IPQ60xx support drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 157 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 3 files changed, 162 insertions(+), 8 deletions(-)