From patchwork Tue Jun 21 08:54:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Baruch Siach X-Patchwork-Id: 12888896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9222DC43334 for ; Tue, 21 Jun 2022 08:56:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=VRQR4SLtJBFoFhyDRuX0LlrN2EcjiZNLT7O0tcwGX6E=; b=eTeq24MQb4tndB MB8DpctkEVTYyhVUK6a2oQ3Dmr6/qs8ahCQlio/ZNguEXIpcH4+oQpYlmhPNgZS3WKfw3dHpd/ASu D3M6grJrxGSM2L50V2MdSwe+nu4BwExZ6CfUSzz8NmXSzyGJ5E2uckUENuW8BhGPbWxZjqN6dDfRJ 8cH0Q8eCB25YobI8dXxTGhNBO41dJXFxh69EF931H99uFZ2YnxEtv8rxyWu8H/GMq2SEoP2+0ZgBc +KJkPzBD8ahjRhQ2ZB57r9sWpb2zV1kZX6xf1fa5HlPCgEW4yljtcDo/yRVPpw4GBhr9+cuH/JV0s 8NkbsLdk1S17rkxpbuLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3ZfX-004RYJ-MV; Tue, 21 Jun 2022 08:55:31 +0000 Received: from guitar.tkos.co.il ([84.110.109.230] helo=mail.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3Zf9-004RRp-Tu for linux-arm-kernel@lists.infradead.org; Tue, 21 Jun 2022 08:55:11 +0000 Received: from tarshish.tkos.co.il (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.tkos.co.il (Postfix) with ESMTPS id 18A8D4407B7; Tue, 21 Jun 2022 11:54:39 +0300 (IDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tkos.co.il; s=default; t=1655801679; bh=kzwDweRYdmF9VZ9rId4uGj3KSP3nY1/NkAN1K4avLsQ=; h=From:To:Cc:Subject:Date:From; b=jLcWXEbf/NvzEGv21abzI5Z0ImDF6d6U41lD5HfZmv3fKmEacgA2j5UMqaY1ewr12 FBjwv9phNqkwWcOG6wuucIvyRgjfq/4m4NCIMFfZYvsFk72Mw24nN4rKSa2cgTJ4XY 1luQcRxwiHVAYluhVbDr0FypGlWxfby6vVALMasuXvmQ1mvXHuBtaZDvGCgemAo/R3 WKg4DG5QoyFa5RQLkaKijdxtnDutlqtL7KhnOQiOEpavvR2JgkKhLN+WgCRVpdtGOB Ru7MRMLxr874+bqp7mDxzAyVyZIZXvuX3PKmz5XgcUGZXZihs+EeJbBTl5Oa6Ys0OR ybhavdFY/qS3Q== From: Baruch Siach To: Andy Gross , Bjorn Andersson , Stanimir Varbanov Cc: Baruch Siach , Kathiravan T , Selvam Sathappan Periakaruppan , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , =?utf-8?q?Pali_Roh=C3=A1r?= , Johan Hovold , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: [PATCH v8 0/3] PCI: IPQ6018 platform support Date: Tue, 21 Jun 2022 11:54:51 +0300 Message-Id: X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_015508_523758_45D06093 X-CRM114-Status: GOOD ( 14.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v8: * Update sign-off addresses to avoid bounce from the defunct codeaurora.org email domain * Add review, ack, and test tags from Rob, Stanimir, and Robert * Drop reset assert on init error path for consistency with deinit * Code formatting cleanup Changes in v7: * Use FIELD_PREP for power limit and scale fields * Add Stanimir Varbanov to Cc * Rebase on v5.19-rc1 Changes in v6: * Drop DT patch applied to the qcom tree * Normalize driver changes subject line * Add a preparatory patch to rename PCIE_CAP_LINK1_VAL to PCIE_CAP_SLOT_VAL, and define it using PCI_EXP_SLTCAP_* macros * Drop a vague comment about ASPM configuration * Add a comment about the source of delay periods Changes in v5: * Remove comments from qcom_pcie_init_2_9_0() (Bjorn Andersson) Changes in v4: * Drop applied DT bits * Add max-link-speed that was missing from the applied v2 patch * Rebase the driver on v5.16-rc3 Changes in v3: * Drop applied patches * Rely on generic code for speed setup * Drop unused macros * Formatting fixes Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (2): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* Selvam Sathappan Periakaruppan (1): PCI: qcom: Add IPQ60xx support drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 147 ++++++++++++++++++- drivers/pci/controller/dwc/pcie-tegra194.c | 6 - 3 files changed, 152 insertions(+), 8 deletions(-)