From patchwork Fri Nov 18 16:44:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 13048470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B28D6C4332F for ; Fri, 18 Nov 2022 16:46:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=HwYpIcTrFlnh5aFLHXOS3KW6WxgWDkgS+Ze1gGYpOJE=; b=eJ12hPn/f1XQdc o7Wt4ruw4/c1FPJA6SZGhuv4bYcpD+Plc1iWO/IawP0gK96Ur1drzF3vnqL2bjDLwPOvvUswjQIPZ H8pPPNZhuwQgES3cEdqBxLxTOmpsL1gi7V0rPNWra5AXgel/TxHPHhfmByNKEcfilLbAQq4V5B5u5 XOGnoT5wkAb6bpdoK2llyWWjGhwxaNbBzWGwlxj5MBz1bkk/Kcvy3DH0V+as4KaKf3gAbWJy33GbD ddhDIJ2MngJYfYZdhKIxTO/3Ue1CeDHXss1mHQBWgnE6F75C21Izzy2oq3+8t1B5/QoZqqu1AFIFE pS7AfB79Xl1pn2vblSNg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ow4Un-005SZ0-L2; Fri, 18 Nov 2022 16:45:41 +0000 Received: from andre.telenet-ops.be ([2a02:1800:120:4::f00:15]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ow4US-005SIM-Cv for linux-arm-kernel@lists.infradead.org; Fri, 18 Nov 2022 16:45:22 +0000 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed10:d0b:c833:41f6:da0e]) by andre.telenet-ops.be with bizsmtp id lslC2800Q29fmst01slCAh; Fri, 18 Nov 2022 17:45:14 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1ow4UK-000pA8-Cx; Fri, 18 Nov 2022 17:45:12 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1ow4UJ-00FrgE-SI; Fri, 18 Nov 2022 17:45:11 +0100 From: Geert Uytterhoeven To: arm-soc , soc Cc: Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [GIT PULL 0/7] Renesas SoC updates for v6.2 (take two) Date: Fri, 18 Nov 2022 17:44:57 +0100 Message-Id: X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221118_084520_612035_000E314E X-CRM114-Status: GOOD ( 18.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi SoC folks, This is my second pull request for the inclusion of Renesas SoC updates for v6.2, and the first one including support for an SoC with a RISC-V CPU core (and including no changes for SoCs with arm32 CPU cores). It consists of 7 parts: [GIT PULL 1/7] Renesas ARM defconfig updates for v6.2 - Enable support for Renesas R-Car S4-8 Spider Ethernet devices in the arm64 defconfig. [GIT PULL 2/7] Renesas ARM DT updates for v6.2 (take two) - Timer (TMU and CMT) and quad Cortex-A76 CPU topology support for the R-Car V4H SoC, - Watchdog, L2 cache, and system controller support for the RZ/V2M SoC on the RZ/V2M Evaluation Kit 2.0, - Ethernet Switch and SERDES supports for the R-Car S4-8 SoC and the Spider development board, - Miscellaneous fixes and improvements. [GIT PULL 3/7] Renesas driver updates for v6.2 (take two) - Add support for identifying the SoC revision on RZ/V2M. [GIT PULL 4/7] Renesas DT binding updates for v6.2 (take two) - Document support for the Andes Technology AX45MP RISC-V CPU Core, as used on the Renesas RZ/Five SoC, - Document support for the Renesas RZ/V2M System Configuration. [GIT PULL 5/7] Renesas RISC-V defconfig updates for v6.2 - Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK board in the risc-v defconfig. [GIT PULL 6/7] Renesas RISC-V DT updates for v6.2 - Add initial support for the Renesas RZ/Five SoC and the Renesas RZ/Five SMARC EVK development board. [GIT PULL 7/7] Renesas RISC-V SoC updates for v6.2 - Add Kconfig option for Renesas RISC-V SoCs. Thanks for pulling! P.S. I'm wondering if I should reduce the number of branches? Probably it would make sense to (at least) use a single branch for the DTS changes, as the RZ/Five DTS files share base SoC and board DTS with RZ/G2UL through #include . Gr{oetje,eeting}s, Geert --- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds