Show patches with: Submitter = Thippeswamy Havalige       |    State = Action Required       |   44 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Thippeswamy Havalige New
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Thippeswamy Havalige New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example increase ecam size value to discover 256 buses during 1 - - --- 2023-10-16 Thippeswamy Havalige New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-o… increase ecam size value to discover 256 buses during - - - --- 2023-10-16 Thippeswamy Havalige New
[v5,RESEND,4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Thippeswamy Havalige New
[v5,RESEND,3/4] PCI: xilinx-nwl: Rename ECAM size default macro ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Thippeswamy Havalige New
[v5,RESEND,2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example ncrease ecam size value to discover 256 buses during 1 - - --- 2023-10-05 Thippeswamy Havalige New
[v5,RESEND,1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-o… ncrease ecam size value to discover 256 buses during - - - --- 2023-10-05 Thippeswamy Havalige New
[v7,RESEND,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-10-03 Thippeswamy Havalige New
[v7,RESEND,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Brid… Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-10-03 Thippeswamy Havalige New
[v7,RESEND,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-10-03 Thippeswamy Havalige New
[v7,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-08-30 Thippeswamy Havalige New
[v7,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-08-30 Thippeswamy Havalige New
[v7,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-08-30 Thippeswamy Havalige New
[v6,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-08-18 Thippeswamy Havalige New
[v6,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-08-18 Thippeswamy Havalige New
[v6,1/3] PCI: xilinx-cpm: Move interrupt bit definitions to common header Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-08-18 Thippeswamy Havalige New
[v5,3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-17 Thippeswamy Havalige New
[v5,2/3] PCI: xilinx-nwl: Rename ECAM size default macro [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-17 Thippeswamy Havalige New
[v5,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example [v5,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example 1 - - --- 2023-08-17 Thippeswamy Havalige New
[v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-17 Thippeswamy Havalige New
[v4,3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-14 Thippeswamy Havalige New
[v4,2/3] PCI: xilinx-nwl: Rename ECAM size default macro. [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-14 Thippeswamy Havalige New
[v4,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example [v4,1/3] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example 1 - - --- 2023-08-14 Thippeswamy Havalige New
[v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-14 Thippeswamy Havalige New
[v3,2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses [v3,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example - - - --- 2023-08-10 Thippeswamy Havalige New
[v3,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example [v3,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example 1 - - --- 2023-08-10 Thippeswamy Havalige New
[v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… [v3] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus… - - - --- 2023-08-10 Thippeswamy Havalige New
[v2,2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses. [v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus … - - - --- 2023-08-08 Thippeswamy Havalige New
[v2,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. [v2,1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. - - - --- 2023-08-08 Thippeswamy Havalige New
[v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus … [v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus … - - - --- 2023-08-08 Thippeswamy Havalige New
[v1,2/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Thippeswamy Havalige New
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Thippeswamy Havalige New
[v1,1/2] PCI: xilinx-nwl: Update ECAM default value and remove unnecessary code. Fix ecam size value to discover 256 buses during - - - --- 2023-08-07 Thippeswamy Havalige New
PCI: xilinx-nwl: Remove unnecessary code and updating ecam default value. PCI: xilinx-nwl: Remove unnecessary code and updating ecam default value. - - - --- 2023-08-03 Thippeswamy Havalige New
[V5,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-06-28 Thippeswamy Havalige New
[V5,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. 1 1 - --- 2023-06-28 Thippeswamy Havalige New
[V5,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-06-28 Thippeswamy Havalige New
[v4,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-31 Thippeswamy Havalige New
[v4,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - 1 - --- 2023-05-31 Thippeswamy Havalige New
[v4,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-31 Thippeswamy Havalige New
[v3,3/3] PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Thippeswamy Havalige New
[v3,2/3] dt-bindings: PCI: xilinx-xdma: Add YAML schemas for Xilinx XDMA PCIe Root Port Bridge Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Thippeswamy Havalige New
[v3,1/3] Move and rename error interrupt bits to a common header. Add support for Xilinx XDMA Soft IP as Root Port. - - - --- 2023-05-19 Thippeswamy Havalige New