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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HtVkQDBabuEV4d48pPsOKc/r4Le52VoO0F6o50VX78ZzbCYo0QG1/PXzW4F3ZS8MAty7DmzKn4Vngj4hSBdw+iEJ4RivSOcEWu6IQjqD2ueAuqrVjdNGnLwoPMwBqvI8N5WK9NwzE0ek/lxVPMYY8QVUrjoE8uPXGaZTT1g4SNUk/AK26En7uwHZIROa54dOcqu0tNqG/WqjO0DVBUGxmNkh1Jhl8Ar/c2aDSBj93/SXOoI/Ox3fMZKq0E7VWh/fO+xPyCRrxJjnb95j1Gi90ilkthYvz9UpWowxdJOG0G6WlC9TfuppQE5dJ0Sb++11Hy2Py33aFskll6Kwao7zGBIuyEoLLEoiNrY8bKTZcnyjaG9EM+LTTJI3mFWGsUkE7dHS+hJJj5PixA+gU+lhFJnmsBGlu2AGax4jbZW9ArreByndwAxXDo8I7D67wDTDmtmntTBzxzEN3L/2TV6WbkPX9AKOG7TZLHc+tG3LY7arKgm9sSdTu1+sDFCmhpQxf3WD1b7qpFWs1DOhq5MuaF6mdOHo6c/6qtWdTtDP+rlLnO0t5e2qIdprsAoJdrYpSM/ROc4TG1sr3eM5+ByC2NxjwR0Cip2XGt0QkJmorTxW/M6wqFN1imzB35AzXzf3W280CjbkGlGLU1CnFHqCqYs+b588gkKCL3SKb4TwNiSNQIY3mnWALYaH/EVlyfREKNfqyzHRs9ub1HtK/88xQ2Ea7vrmMjwa+6x/GxmIVFg4xDHjFHt94ndolMO0RZQ+duH++fDC9DWSIVbnYYdnmvUUQi4CcKjBHcYQEQRRxfKuvEoHPCfFmEBqtNAcNQSpEzfKfIrmOu/gsZ8RvPZXzs5rrQKcLTZQXi3F4HekRUH5W4ejfd9UcMsT0LqQJIfYxJDl8io+4VwzITnxkAmfMIoXAxD4me5e0MlJzDZRvRZQBx/P8r1TXvD2wOK5+QnlGp1CSBjYiONZUxGVA6rvw+aJgq4QvL4PvC8ecY/3uQNY8x+qi5RIE1e0ahsb/9+MHUGEdKNuFi9PPVAHx62gWY9knUWzRYEfK6iH6fFrJxALM11LqL73sw4cCmummFpXeZlkt09ePQXiE3M+aZtBIeYWKHqcitzkTrghcwGjQyU1AKN2oLVtTUDACrI4IgKa85HZprgExf5VwH+b1CDGLqtu0l0oD2BYNd8LwEzslWMH3llg6HvCboAdZzByCdXndADANvdDvnN9O6Q3RKtS3i1L8UAzJZKGZfS/fIh4krYBp1uPVOaX1dMGDs0qHB6d0462uJ+Jlsji3KFXaLfh+LUhEm6GIXlt/7uRTbbEUk1sIkfwV9VHmjV8tfJx2f41wXM/6TJV85lywOUd6TvYi1XeQWKKGkaRNWpRWdQpknatOm8rbsqEMXTafCtH7bjk7y+hf6LJ9uig8Y9uQCQMRftXc6gWlFo8CK+lLT5cV/WzLAQYwrJofdIxXGNXF3bkwfmVg6CFWdNlIWqx/IJT42aVFU6RGXKvytd8LnqmCGjuK38CsGSmg5mCAoQnje9Dz8RNhv/aZkeVU1jLCJPL19qQ4z3kUtNu/ZBzKx0vocs= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: aa4154a6-9451-44c3-e4c4-08dc23fb2c24 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2024 14:28:06.5680 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NQKwJMeARC/Row0c/ZMYdNvUr5y2H6sC0k9wWTWhqqIsI6YBgoZk1WnXaipDU8b/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4524 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240202_062824_467648_29B07D72 X-CRM114-Status: GOOD ( 15.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If the SMMU is configured to use a two level CD table then arm_smmu_write_ctx_desc() allocates a CD table leaf internally using GFP_KERNEL. Due to recent changes this is being done under a spinlock to iterate over the device list - thus it will trigger a sleeping while atomic warning: arm_smmu_sva_set_dev_pasid() mutex_lock(&sva_lock); __arm_smmu_sva_bind() arm_smmu_mmu_notifier_get() spin_lock_irqsave() arm_smmu_write_ctx_desc() arm_smmu_get_cd_ptr() arm_smmu_alloc_cd_leaf_table() dmam_alloc_coherent(GFP_KERNEL) This is a 64K high order allocation and really should not be done atomically. The proper answer is to sequence CD programming in a way that does not require the device list or a spinlock. Part two of my lager series does this and already solves this bug. In the mean time we can solve the functional issue by preallocating the CD entry outside any locking. CD leafs are effectively never freed so this guarantees the arm_smmu_write_ctx_desc() inside the lock will not take the allocation path. Fixes: 24503148c545 ("iommu/arm-smmu-v3: Refactor write_ctx_desc") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/all/4e25d161-0cf8-4050-9aa3-dfa21cd63e56@moroto.mountain/ Signed-off-by: Jason Gunthorpe Reviewed-by: Michael Shavit --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 3 files changed, 8 insertions(+), 1 deletion(-) base-commit: c76c50cd425e574df5a071cd7e1805d0764aabff diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 05722121f00e70..068d60732e6481 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -588,6 +588,11 @@ static int arm_smmu_sva_set_dev_pasid(struct iommu_domain *domain, { int ret = 0; struct mm_struct *mm = domain->mm; + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + + /* Preallocate the required leafs outside locks */ + if (!arm_smmu_get_cd_ptr(master, id)) + return -ENOMEM; mutex_lock(&sva_lock); ret = __arm_smmu_sva_bind(dev, mm); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 0ffb1cf17e0b2e..ec2bb8685bb50e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1019,7 +1019,7 @@ static void arm_smmu_write_cd_l1_desc(__le64 *dst, WRITE_ONCE(*dst, cpu_to_le64(val)); } -static __le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) +__le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid) { __le64 *l1ptr; unsigned int idx; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 65fb388d51734d..fa0eeb3519ef28 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -748,6 +748,8 @@ extern struct xarray arm_smmu_asid_xa; extern struct mutex arm_smmu_asid_lock; extern struct arm_smmu_ctx_desc quiet_cd; +__le64 *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid); + int arm_smmu_write_ctx_desc(struct arm_smmu_master *smmu_master, int ssid, struct arm_smmu_ctx_desc *cd); void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid);