From patchwork Wed Jul 22 13:17:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 6843571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D0B7DC05AC for ; Wed, 22 Jul 2015 13:19:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CB12120544 for ; Wed, 22 Jul 2015 13:19:32 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D203206E4 for ; Wed, 22 Jul 2015 13:19:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZHtu2-0006t2-FO; Wed, 22 Jul 2015 13:17:42 +0000 Received: from eusmtp01.atmel.com ([212.144.249.243]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZHttz-0006nC-D8; Wed, 22 Jul 2015 13:17:40 +0000 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Wed, 22 Jul 2015 15:17:14 +0200 From: Cyrille Pitchen To: , , , , , , , , , , Subject: [PATCH v2 1/5] mtd: spi-nor: notify (Q)SPI controller about protocol change Date: Wed, 22 Jul 2015 15:17:06 +0200 Message-ID: <036f143509fed3f303508d1688d68012790f835a.1437569902.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150722_061739_833780_AE48B80E X-CRM114-Status: GOOD ( 11.94 ) X-Spam-Score: -5.4 (-----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mtd@lists.infradead.org, galak@codeaurora.org, Cyrille Pitchen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Once the Quad SPI mode has been enabled on a Micron flash memory, this device expects ALL the following commands to use the SPI 4-4-4 protocol. The (Q)SPI controller needs to be notified about the protocol change so it can adapt and keep on dialoging with the Micron memory. Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 17 +++++++++++++++++ include/linux/mtd/spi-nor.h | 13 +++++++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d78831b4422b..93627d4e6be8 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -163,6 +163,18 @@ static inline int write_disable(struct spi_nor *nor) return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0); } +/* + * Notify the (Q)SPI controller about the new protocol to be used. + */ +static inline int spi_nor_set_protocol(struct spi_nor *nor, + enum spi_protocol proto) +{ + if (nor->set_protocol) + return nor->set_protocol(nor, proto); + + return 0; +} + static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; @@ -943,6 +955,11 @@ static int micron_quad_enable(struct spi_nor *nor) return ret; } + /* switch protocol to Quad CMD 4-4-4 */ + ret = spi_nor_set_protocol(nor, SPI_PROTO_4_4_4); + if (ret) + return ret; + ret = spi_nor_wait_till_ready(nor); if (ret) return ret; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e5409524bb0a..1bf6f11310ef 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -87,6 +87,16 @@ enum read_mode { SPI_NOR_QUAD, }; +enum spi_protocol { + SPI_PROTO_1_1_1, /* SPI */ + SPI_PROTO_1_1_2, /* Dual Output */ + SPI_PROTO_1_1_4, /* Quad Output */ + SPI_PROTO_1_2_2, /* Dual IO */ + SPI_PROTO_1_4_4, /* Quad IO */ + SPI_PROTO_2_2_2, /* Dual Command */ + SPI_PROTO_4_4_4, /* Quad Command */ +}; + /** * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer * @wren: command for "Write Enable", or 0x00 for not required @@ -149,6 +159,7 @@ enum spi_nor_option_flags { * read/write/erase/lock/unlock operations * @read_xfer: [OPTIONAL] the read fundamental primitive * @write_xfer: [OPTIONAL] the writefundamental primitive + * @set_protocol: [OPTIONAL] notify about protocol change * @read_reg: [DRIVER-SPECIFIC] read out the register * @write_reg: [DRIVER-SPECIFIC] write data to the register * @read: [DRIVER-SPECIFIC] read data from the SPI NOR @@ -185,6 +196,8 @@ struct spi_nor { int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len, int write_enable); + int (*set_protocol)(struct spi_nor *nor, enum spi_protocol proto); + int (*read)(struct spi_nor *nor, loff_t from, size_t len, size_t *retlen, u_char *read_buf); void (*write)(struct spi_nor *nor, loff_t to,