Message ID | 082c3040e2be27d30e0642943f6df35ff4de5666.1524816502.git.sean.wang@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Fri, Apr 27, 2018 at 04:14:44PM +0800, sean.wang@mediatek.com wrote: > From: Sean Wang <sean.wang@mediatek.com> > > Just add binding for a required clock referenced by Mali-450 on MT7623 > or MT2701 SoC. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > --- > include/dt-bindings/clock/mt2701-clk.h | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org>
Quoting sean.wang@mediatek.com (2018-04-27 01:14:44) > From: Sean Wang <sean.wang@mediatek.com> > > Just add binding for a required clock referenced by Mali-450 on MT7623 > or MT2701 SoC. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Sean Wang <sean.wang@mediatek.com> > --- Applied to clk-next
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 24e93df..2ac62a6 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -431,6 +431,10 @@ #define CLK_ETHSYS_CRYPTO 8 #define CLK_ETHSYS_NR 9 +/* G3DSYS */ +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + /* BDP */ #define CLK_BDP_BRG_BA 1