From patchwork Thu Jan 31 00:40:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hyok S. Choi" X-Patchwork-Id: 2070311 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 444AC3FD1A for ; Thu, 31 Jan 2013 00:42:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U0iCb-0005P8-40; Thu, 31 Jan 2013 00:40:29 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U0iCV-0005O2-TA for linux-arm-kernel@lists.infradead.org; Thu, 31 Jan 2013 00:40:26 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHG00FXDSI5RT60@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 31 Jan 2013 09:40:19 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.46]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id D7.13.03918.27DB9015; Thu, 31 Jan 2013 09:40:18 +0900 (KST) X-AuditID: cbfee61a-b7f7d6d000000f4e-4b-5109bd724efd Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 16.13.03918.27DB9015; Thu, 31 Jan 2013 09:40:18 +0900 (KST) Received: from DOHYOKCHOI03 ([168.219.193.154]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHG00NYRSJ62JB1@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 31 Jan 2013 09:40:18 +0900 (KST) From: "Hyok S. Choi" To: 'Will Deacon' , linux-arm-kernel@lists.infradead.org References: <1359556069-28289-1-git-send-email-will.deacon@arm.com> <1359556069-28289-3-git-send-email-will.deacon@arm.com> In-reply-to: <1359556069-28289-3-git-send-email-will.deacon@arm.com> Subject: RE: [PATCH 2/6] ARM: cache: remove ARMv3 support code Date: Thu, 31 Jan 2013 09:40:18 +0900 Organization: Samsung Electronics Message-id: <0a6801cdff4b$8ae22940$a0a67bc0$@samsung.com> MIME-version: 1.0 X-Mailer: Microsoft Outlook 14.0 Thread-index: AQLJJ3uj7NSS9TPPu2e4X5SSJ1VXjgHeqPrull1RajA= Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsVy+t8zPd2ivZyBBmteSVlsenyN1YHRY/OS +gDGKC6blNSczLLUIn27BK6MGX9+MhfMMalY+2wOUwPjH80uRk4OCQETidlr5jNC2GISF+6t Z+ti5OIQEljGKHHr+DZGmKK/TX+ZIBLTGSUutR9jgXBWMEnMa/vMDlIlJCAvcfXFPzYQm01A R2LZi2tgcREBX4l5nd9YQGxmAVWJ1l2zWCHqayVenOtgBrE5BVwk5py9BtTLwSEsYCfx50sI SJgFqLzt6hImEJtfQFHi6o/HYAfxClhK9J26xQRhC0r8mHwParyWxPqdx5kgbHmJzWveMkM8 oCCx4+xrRohzrCTu//4OVS8ise/FO0aQXyQEtrFL/NpxiRlisYDEt8mHWEDukRCQldh0AGqO pMTBFTdYJjBKzUKyehaS1bOQrJ6FZMUCRpZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGCGx KLWDcWWDxSFGAQ5GJR5eDUfOQCHWxLLiytxDjBIczEoivIdMgEK8KYmVValF+fFFpTmpxYcY k4GOncgsJZqcD0wTeSXxhsYGxoaGloZmppamBqQJK4nzMp56EiAkkJ5YkpqdmlqQWgSzhYmD U6qB8cJLBaWnGx4UVS8suPN3bb/+/aINygqfSs/GHug8/vx0Qptxi/7jh7LF5j0rc2N3r760 uXyq8P2L77IV5OYdVPHufPSAZ+Y8rq11pueKn632jHGS9j1lmO3y+O6C1ADWMIVzVyrvL/6m NIW929Xm/P1mL8vVvsYHdm6sXnJMduPef20qS9kc/ZRYijMSDbWYi4oTAT/bFnAJAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKKsWRmVeSWpSXmKPExsVy+t9jQd2ivZyBBgcuilhsenyN1YHRY/OS +gDGqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg qUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwjrGjBl/fjIXzDGpWPtsDlMD 4x/NLkZODgkBE4m/TX+ZIGwxiQv31rN1MXJxCAlMZ5S41H6MBcJZwSQxr+0zO0iVkIC8xNUX /9hAbDYBHYllL66BxUUEfCXmdX5jAbGZBVQlWnfNYoWor5V4ca6DGcTmFHCRmHP2GlAvB4ew gJ3Eny8hIGEWoPK2q0vAjuAXUJS4+uMxI4jNK2Ap0XfqFhOELSjxY/I9qPFaEut3HmeCsOUl Nq95ywzxgILEjrOvGSHOsZK4//s7VL2IxL4X7xgnMIrMQjJqFpJRs5CMmoWkZQEjyypG0dSC 5ILipPRcQ73ixNzi0rx0veT83E2M4Eh/JrWDcWWDxSFGAQ5GJR5eDUfOQCHWxLLiytxDjBIc zEoivIdMgEK8KYmVValF+fFFpTmpxYcYk4G+nsgsJZqcD0xCeSXxhsYmZkaWRmbGJubGxqQJ K4nzMp56EiAkkJ5YkpqdmlqQWgSzhYmDU6qBUUvnG0v+54VzdrGyuWdFztvKfnO9uGhH0dbS k16SKRFdj3k3vH44cVqv6/O9qW/zIxQyvjJ+Vr9nx3RAmfeQVtqZj33nnllGHekqX/d00y1+ 25t1clpPVppb/r9hFWzUqrhtytKfstcj039OSXaJsfcLs9n2hMHAt8oysO5U7D75j6XHvyvK KbEUZyQaajEXFScCAKiMMWk4AwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130130_194024_454793_223E4D8A X-CRM114-Status: GOOD ( 19.66 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.34 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: 'Greg Ungerer' X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list Reply-To: hyok.choi@samsung.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org I know there is no v3 architecture in current platforms in mainline tree, but can we _remove_ v3 support codes? IOW, Is there no platform port users for ARM7 nommu families(such as ARM700 or ARM710)? -----Original Message----- From: Will Deacon [mailto:will.deacon@arm.com] Sent: Wednesday, January 30, 2013 11:28 PM To: linux-arm-kernel@lists.infradead.org Cc: Will Deacon; Hyok S. Choi; Greg Ungerer Subject: [PATCH 2/6] ARM: cache: remove ARMv3 support code This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Cc: Hyok S. Choi Cc: Greg Ungerer Signed-off-by: Will Deacon --- arch/arm/include/asm/glue-cache.h | 8 --- arch/arm/mm/Kconfig | 5 +- arch/arm/mm/Makefile | 1 - arch/arm/mm/cache-v3.S | 137 -------------------------------------- arch/arm/mm/proc-arm740.S | 2 +- 5 files changed, 2 insertions(+), 151 deletions(-) delete mode 100644 arch/arm/mm/cache-v3.S -- 1.8.0 diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index cca9f15..ea289e1 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -19,14 +19,6 @@ #undef _CACHE #undef MULTI_CACHE -#if defined(CONFIG_CPU_CACHE_V3) -# ifdef _CACHE -# define MULTI_CACHE 1 -# else -# define _CACHE v3 -# endif -#endif - #if defined(CONFIG_CPU_CACHE_V4) # ifdef _CACHE # define MULTI_CACHE 1 diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 3fd629d..c430f46 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -43,7 +43,7 @@ config CPU_ARM740T depends on !MMU select CPU_32v4T select CPU_ABRT_LV4T - select CPU_CACHE_V3 # although the core is v4t + select CPU_CACHE_V4 select CPU_CP15_MPU select CPU_PABRT_LEGACY help @@ -469,9 +469,6 @@ config CPU_PABRT_V7 bool # The cache model -config CPU_CACHE_V3 - bool - config CPU_CACHE_V4 bool diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 8a9c4cb..c0fd3c1 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o -obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S deleted file mode 100644 index 8a3fade..0000000 --- a/arch/arm/mm/cache-v3.S +++ /dev/null @@ -1,137 +0,0 @@ -/* - * linux/arch/arm/mm/cache-v3.S - * - * Copyright (C) 1997-2002 Russell king - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include "proc-macros.S" - -/* - * flush_icache_all() - * - * Unconditionally clean and invalidate the entire icache. - */ -ENTRY(v3_flush_icache_all) - mov pc, lr -ENDPROC(v3_flush_icache_all) - -/* - * flush_user_cache_all() - * - * Invalidate all cache entries in a particular address - * space. - * - * - mm - mm_struct describing address space - */ -ENTRY(v3_flush_user_cache_all) - /* FALLTHROUGH */ -/* - * flush_kern_cache_all() - * - * Clean and invalidate the entire cache. - */ -ENTRY(v3_flush_kern_cache_all) - /* FALLTHROUGH */ - -/* - * flush_user_cache_range(start, end, flags) - * - * Invalidate a range of cache entries in the specified - * address space. - * - * - start - start address (may not be aligned) - * - end - end address (exclusive, may not be aligned) - * - flags - vma_area_struct flags describing address space - */ -ENTRY(v3_flush_user_cache_range) - mov ip, #0 - mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache - mov pc, lr - -/* - * coherent_kern_range(start, end) - * - * Ensure coherency between the Icache and the Dcache in the - * region described by start. If you have non-snooping - * Harvard caches, you need to implement this function. - * - * - start - virtual start address - * - end - virtual end address - */ -ENTRY(v3_coherent_kern_range) - /* FALLTHROUGH */ - -/* - * coherent_user_range(start, end) - * - * Ensure coherency between the Icache and the Dcache in the - * region described by start. If you have non-snooping - * Harvard caches, you need to implement this function. - * - * - start - virtual start address - * - end - virtual end address - */ -ENTRY(v3_coherent_user_range) - mov r0, #0 - mov pc, lr - -/* - * flush_kern_dcache_area(void *page, size_t size) - * - * Ensure no D cache aliasing occurs, either with itself or - * the I cache - * - * - addr - kernel address - * - size - region size - */ -ENTRY(v3_flush_kern_dcache_area) - /* FALLTHROUGH */ - -/* - * dma_flush_range(start, end) - * - * Clean and invalidate the specified virtual address range. - * - * - start - virtual start address - * - end - virtual end address - */ -ENTRY(v3_dma_flush_range) - mov r0, #0 - mcr p15, 0, r0, c7, c0, 0 @ flush ID cache - mov pc, lr - -/* - * dma_unmap_area(start, size, dir) - * - start - kernel virtual start address - * - size - size of region - * - dir - DMA direction - */ -ENTRY(v3_dma_unmap_area) - teq r2, #DMA_TO_DEVICE - bne v3_dma_flush_range - /* FALLTHROUGH */ - -/* - * dma_map_area(start, size, dir) - * - start - kernel virtual start address - * - size - size of region - * - dir - DMA direction - */ -ENTRY(v3_dma_map_area) - mov pc, lr -ENDPROC(v3_dma_unmap_area) -ENDPROC(v3_dma_map_area) - - .globl v3_flush_kern_cache_louis - .equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all - - __INITDATA - - @ define struct cpu_cache_fns (see and proc-macros.S) - define_cache_functions v3 diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index dc5de5d..2088234 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -145,5 +145,5 @@ __arm740_proc_info: .long arm740_processor_functions .long 0 .long 0 - .long v3_cache_fns @ cache model + .long v4_cache_fns @ cache model .size __arm740_proc_info, . - __arm740_proc_info