@@ -19,6 +19,16 @@
cpu-supply = <&sw1a_reg>;
};
+&gpio2 {
+ /* Configured as pullup by QSPI pin group */
+ qspi-reset-hog {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "qspi-reset";
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -160,6 +170,25 @@
>;
};
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
+ MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
+ MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
+ MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
+ MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
+ MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
+ MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
+ >;
+ };
+
+ pinctrl_qspi_reset: qspi_resetgrp {
+ fsl,pins = <
+ /* #QSPI_RESET */
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
+ >;
+ };
+
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
@@ -217,6 +246,20 @@
};
};
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <29000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+};
+
&sdma {
status = "okay";
};
The SPI-NOR flash on the SoM was missing from the device tree. The TQMa7 as a designated QSPI_RESET# pin, however depending on the hardware configuration the pin may be unconnected, or be used for a different purpose. With this in mind, we mux the pin as a pullup and define an input hog for it, but keep it a separate pin group, so that it is easy for dependent Device Trees to modify the configuration. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> --- v2: - Add input hog for reset pin and move to separate pin group, explain in commit message. - Update flash node for modern "partitions" specification arch/arm/boot/dts/imx7-tqma7.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+)