From patchwork Mon Feb 4 22:25:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kgene@kernel.org X-Patchwork-Id: 2095311 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 84E2EDFE82 for ; Mon, 4 Feb 2013 22:29:01 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U2UUD-0004p8-SC; Mon, 04 Feb 2013 22:26:01 +0000 Received: from mailout4.samsung.com ([203.254.224.34]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U2UU9-0004oC-68 for linux-arm-kernel@lists.infradead.org; Mon, 04 Feb 2013 22:25:59 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHP0032YVMYKT80@mailout4.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 05 Feb 2013 07:25:51 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 47.A6.03880.F6530115; Tue, 05 Feb 2013 07:25:51 +0900 (KST) X-AuditID: cbfee61b-b7fb06d000000f28-1f-5110356f4400 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C6.A6.03880.E6530115; Tue, 05 Feb 2013 07:25:50 +0900 (KST) Received: from visitor4lab ([105.128.18.157]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHP0047GVMZVP10@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Tue, 05 Feb 2013 07:25:50 +0900 (KST) From: kgene@kernel.org To: 'Santosh Shilimkar' , 'Benoit Cousson' References: <1358818887-16870-1-git-send-email-kgene.kim@samsung.com> <20130122101554.GA18876@e106331-lin.cambridge.arm.com> <063f01cdf8ec$926cda30$b7468e90$@samsung.com> <20130123103614.GD32237@e106331-lin.cambridge.arm.com> <50FFC1B0.8000601@ti.com> <51012C4B.5080300@ti.com> <51013432.3080903@arm.com> <5108C9C9.4010409@ti.com> In-reply-to: <5108C9C9.4010409@ti.com> Subject: RE: [PATCH] ARM: dts: specify all the per-cpu interrupts of arch timer for exynos5440 Date: Mon, 04 Feb 2013 14:25:37 -0800 Message-id: <11ec01ce0326$90bcb590$b23620b0$@kernel.org> MIME-version: 1.0 X-Mailer: Microsoft Outlook 14.0 Thread-index: AQMTjt4PWHFOh1YJzH1i6AX6HVGa9ADrkQcyAkqZhbMB6Ay6cgI5XIHZAmaSrRsCZC3N0wGK0pMelXHErEA= Content-language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t8zY918U4FAg+/vzC02Pb7G6sDosXlJ fQBjFJdNSmpOZllqkb5dAlfGr737mQou6lSc+TSJuYFxvVIXIyeHhICJRMesDYwQtpjEhXvr 2boYuTiEBJYxSkz+fooJpmj/vIeMEIlFjBLdk/+wQlUxSbz8dxjI4eBgA2qf+kQapEFYQEti 4ZYmFhBbRCBS4sK3KWAbmAVuMkmsOmsD0XuFSWLx4aVgRZwCahKzfx1mgmhOkFjetgesgUVA VeLnw+VgNbwCFhI/5hxkhbAFJX5MvscCMVRLYv3O40wQtrzE5jVvmSGuVpDYcfY1I8QRKRKt dzeyQ9SIS0x68JAd5AgJgVXsElNvv2WBWCYg8W3yIRaQZyQEZCU2HYCaIylxcMUNlgmMkrOQ rJ6FZPUsJKtnIVmxgJFlFaNoakFyQXFSeq6RXnFibnFpXrpecn7uJkZI1EnvYFzVYHGIUYCD UYmH98dl/kAh1sSy4srcQ4wSHMxKIrwfbwCFeFMSK6tSi/Lji0pzUosPMSYDHTuRWUo0OR+Y EPJK4g2NjU3MTExNzC1NzU1JE1YS52U89SRASCA9sSQ1OzW1ILUIZgsTB6dUA6PL2gePhRur dar4/zzIvJMuJqsrw/Qs62GR7q/bDCJTzhrdd+jMYr53PnLD1JzpCyvmKBfPjRSWUz4Y/sNt Ub76j0imzuq/a4tVJnMFH9tQbBdd3P58uuDzju7vn7LiK4yPqPP0Lpnj4bB6yc2v3hM35Dov /O1qHPn0IFPTrW/J1qr7T4b/uaDEUpyRaKjFXFScCACFRoYi/gIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFKsWRmVeSWpSXmKPExsVy+t9jAd08U4FAg4b5uhabHl9jdWD02Lyk PoAxqoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwdo qpJCWWJOKVAoILG4WEnfDtOE0BA3XQuYxghd35AguB4jAzSQsI4x49fe/UwFF3UqznyaxNzA uF6pi5GTQ0LARGL/vIeMELaYxIV769m6GLk4hAQWMUp0T/7DCuEsY5J4+e8wkMPBwQZUNfWJ NEiDsICWxMItTSwgtohApMSFb1PABjEL3GSSWHXWBqL3CpPE4sNLwYo4BdQkZv86zATRnCCx vG0PWAOLgKrEz4fLwWp4BSwkfsw5yAphC0r8mHyPBWKolsT6nceZIGx5ic1r3jJDXK0gsePs a0aII1IkWu9uZIeoEZeY9OAh+wRG4VlIRs1CMmoWklGzkLQsYGRZxSiaWpBcUJyUnmukV5yY W1yal66XnJ+7iREc08+kdzCuarA4xCjAwajEw/vjMn+gEGtiWXFl7iFGCQ5mJRHejzeAQrwp iZVVqUX58UWlOanFhxiTgT6dyCwlmpwPTDd5JfGGxiZmRpZGZhZGJubmpAkrifMynnoSICSQ nliSmp2aWpBaBLOFiYNTqoGx2GFCJlfn15VaQaoOvbvSra+sdex3F7xh8OvRzEc7za7n5U5e JbZSr3H2atHJtb6fOBl8nnncExb6uf1UtMoWpmMPasSsosNPiP3zDPSpcIjeqxBVyJjff/vl 11d3XqmETSzK28n69JnVpBdHlz873vCpacu/72ey6h4+cVjy56LNr23t02xtlFiKMxINtZiL ihMBPEr/Mi0DAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130204_172557_719215_3B0D7A37 X-CRM114-Status: GOOD ( 36.93 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.34 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: 'Mark Rutland' , linux-samsung-soc@vger.kernel.org, 'Marc Zyngier' , devicetree-discuss@lists.ozlabs.org, rob.herring@calxeda.com, 'Grant Likely' , 'Tony Lindgren' , 'Thomas Abraham' , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Santosh Shilimkar wrote: > > Benoit, > > On Thursday 24 January 2013 06:46 PM, Marc Zyngier wrote: > > Hi Benoit, > > > > On 24/01/13 12:42, Benoit Cousson wrote: > >> Hi Santosh, > >> > >> On 01/23/2013 11:55 AM, Santosh Shilimkar wrote: > >>> Looping Marc, Benoit > >>> > >>> On Wednesday 23 January 2013 04:06 PM, Mark Rutland wrote: > >>>> On Tue, Jan 22, 2013 at 10:05:18PM +0000, Kukjin Kim wrote: > >>>>> Mark Rutland wrote: > >>>>>> > >>>>> + devicetree-discuss, Grant Likely, Rob Herring and Tony Lindgren > >>>>> > >>>>>> On Tue, Jan 22, 2013 at 01:41:27AM +0000, Kukjin Kim wrote: > >>>>>>> From: Thomas Abraham > >>>>>>> > >>>>>>> Need to be changed requirements in the 'cpus' node for > exynos5440 > >>>>>>> to specify all the per-cpu interrupts of arch timer. > >>>>>> > >>>>>> The node(s) for the arch timer should not be in the cpus/cpu@N > nodes. > >>>>>> Instead, there should be one node (in the root of the tree). > >>>>>> > >>>>> Well, I don't think so. As per my understanding, the local timers are > >>>>> attached to every ARM cores (cpus) and it generates certain interrupt > >>>>> to the > >>>>> GIC. So the correct representation for this in device tree is to > >>>>> include the > >>>>> interrupts in the cpu nodes in dts file. Your comments refer to a > >>>>> limitation in the Linux kernel implementation of the arch_timer and it > >>>>> should not result in representing the hardware details incorrectly in > >>>>> the > >>>>> dts file. > >>>> > >>>> I disagree. The "correct representation" is whatever the devicetree > >>>> binding > >>>> documentation describes. It does not describe placing timer nodes in > >>>> the cpu > >>>> nodes. > >>>> > >>> This seems to be exact same topic what is getting discussed here [1] > >>> Technically DT is suppose to represent how the hardware is rather than > >>> how the bindings are done. > >>> > >>> But as Marc pointed out, the approach taken currently is to not > >>> duplicate the banked information. The thread [1] isn't concluded > >>> yet but looks like we might want to avoid duplicating the information > >>> considering, more of such duplication needs to follow. e.g gic i/f > >>> > >>> Am still waiting on what Benoit has to say ? > >> > >> I agree with you :-) > >> > >> I'm not sure the binding was properly done to reflect the HW accurately. > >> > >> A local timer for my point of view should be located in the cpu node > >> like a L1 cache. Or at least referenced in each cpu by a phandle. > >> > >> What was the rational to put it in the root? > > > > The rational was to follow what we already do for most (all?) banked > > resources. We already have TWD, GIC and PMU that have a root node, > > avoiding duplicated resources. I think consistency is an important thing > > to have. > > > > If we decide to move everything into CPU nodes and duplicate all the > > banked resources, fine. But that has impacts that reach far beyond the > > simple case of the timer. > > > > In particular, good luck with the GIC distributor interface, where the > > 32 first interrupts are per CPU. This would also mandate a redesign of > > the way we specify a PPI, as the CPU mask in the third field doesn't > > mean a thing anymore. > > > > If you insist on having a phandle to a timer node, fine by me. > > > Can you please comment on it so that we can conclude this thread ? > I would like to update my patches and hence the push. > Hmm...it's time to decide for now. Let me add timer node for ARM arch timer at this moment. Then if any change is required, will do it later. If any objection, let me know. If not, I will queue following patch for v3.9. Thanks. - Kukjin ---------8<------------------------------8<--------------------------------- - From: Kukjin Kim Subject: [PATCH] ARM: dts: re-organized cpu node for exynos5440 This patch adds timer node and re-organizes cpu node for exynos5440. Acked-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5440.dtsi | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 1e7a2b0..5c5a699 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -24,40 +24,37 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>; - clock-frequency = <1000000>; - }; + reg = <0>; }; cpu@1 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <1>; }; cpu@2 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <2>; }; cpu@3 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <3>; }; }; + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + clock-frequency = <50000000>; + }; + serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>;