From patchwork Thu Jul 16 15:27:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyrille Pitchen X-Patchwork-Id: 6808291 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DFB759F536 for ; Thu, 16 Jul 2015 15:30:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 11776205E6 for ; Thu, 16 Jul 2015 15:30:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B33F205B8 for ; Thu, 16 Jul 2015 15:30:39 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZFl5n-0001TH-EZ; Thu, 16 Jul 2015 15:28:59 +0000 Received: from eusmtp01.atmel.com ([212.144.249.243]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZFl4t-0000cZ-F7; Thu, 16 Jul 2015 15:28:04 +0000 Received: from tenerife.corp.atmel.com (10.161.101.13) by eusmtp01.atmel.com (10.161.101.31) with Microsoft SMTP Server id 14.3.235.1; Thu, 16 Jul 2015 17:27:45 +0200 From: Cyrille Pitchen To: , , , , , , , , , , Subject: [PATCH 5/7] mtd: spi-nor: allow the set the latency code on Spansion memories Date: Thu, 16 Jul 2015 17:27:52 +0200 Message-ID: <12f0bceb57e1bf25279a995f76103b4e75091e82.1437059658.git.cyrille.pitchen@atmel.com> X-Mailer: git-send-email 1.8.2.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150716_082803_885854_CB203E58 X-CRM114-Status: GOOD ( 11.01 ) X-Spam-Score: -5.5 (-----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mtd@lists.infradead.org, galak@codeaurora.org, Cyrille Pitchen , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Both the SPI controller and the flash memory must agree on the number of dummy cycles to use for Fast Read commands. For Spansion memories, this number of dummy cycles is configured through a so called latency code in their Control Register. The right latency code can be found in the memory datasheet and depends on the SPI clock frequency, the op code of the Fast Read command and the Single/Dual Data Rate mode. Signed-off-by: Cyrille Pitchen --- drivers/mtd/spi-nor/spi-nor.c | 46 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 5df6e4712a9e..32fddf06da3f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -989,6 +989,50 @@ static int set_quad_mode(struct spi_nor *nor, struct flash_info *info) } } +static int spansion_set_latency_code(struct spi_nor *nor) +{ + struct device_node *np = nor->dev->of_node; + u8 cr, mask = GENMASK(7, 6); + u32 lc; + int ret; + + if (!np || of_property_read_u32(np, "spansion,latency-code", &lc)) + return 0; + + if (lc & ~(mask >> 6)) { + dev_err(nor->dev, "invalid latency code: %u\n", lc); + return -EINVAL; + } + + ret = read_cr(nor); + if (ret < 0) { + dev_err(nor->dev, + "error while reading configuration register\n"); + return ret; + } + + write_enable(nor); + + cr = ret; + cr &= ~mask; + cr |= (lc << 6); + ret = write_sr_cr(nor, cr << 8); + if (ret < 0) { + dev_err(nor->dev, + "error while updating configuration register\n"); + return -EINVAL; + } + + /* read back and check it */ + ret = read_cr(nor); + if (!(ret >= 0 && (ret & mask) == (lc << 6))) { + dev_err(nor->dev, "Spansion latency code not set\n"); + return -EINVAL; + } + + return 0; +} + static int micron_set_dummy_cycles(struct spi_nor *nor) { int ret; @@ -1045,6 +1089,8 @@ static int spi_nor_read_dummy_cycles(struct spi_nor *nor, * backward compatibility. */ switch (JEDEC_MFR(info)) { + case CFI_MFR_AMD: + return spansion_set_latency_code(nor); case CFI_MFR_ST: return micron_set_dummy_cycles(nor); default: