From patchwork Fri May 27 22:10:10 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Kukjin X-Patchwork-Id: 825592 Received: from bombadil.infradead.org (173-166-109-252-newengland.hfc.comcastbusiness.net [173.166.109.252]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p4RMHiZG006985 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 27 May 2011 22:18:06 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by bombadil.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QQ5Ew-0005fA-Kx; Fri, 27 May 2011 22:10:42 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QQ5Eu-00085j-80; Fri, 27 May 2011 22:10:40 +0000 Received: from mail-pz0-f49.google.com ([209.85.210.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QQ5Ef-00084p-HT for linux-arm-kernel@lists.infradead.org; Fri, 27 May 2011 22:10:26 +0000 Received: by pzk28 with SMTP id 28so1104939pzk.36 for ; Fri, 27 May 2011 15:10:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:cc:subject:date:message-id :x-mailer:in-reply-to:references; bh=em0T6G1mrTJwTjJiXJIUzgx/BV1IB5tW23tzLArrXsY=; b=DkawgITvPQguNld4TAqB41L7HYaBLwmMBgxGt1XYtp1AriVW1uGCZGIOfM/OdnBS+N M8Dc1VWH2tDJT6XTn5GkSKITQiWdbR62iHi1KZFlbPRLRNEHVgXIhFuKHhNGUxJQk/nq ET5lPhKDnyPzaXFRoILfXIBnUTxSDicl+7YH0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; b=BoB6qNrIskLPZ8s4ee9jPBmHD0zcFCzEP84gLlkxvtmmu9h5m9tzybYOID/BqtD4g2 CTnaNOOP2czy8RpMKuFNPKXDsPM5L3Opuj5XKHC3OaQhLX/n+dJ3P2EoQMEK0LVqfuRV loR/6REcm30cjz+Pjda7nqww6GxsKLyv7aGPU= Received: by 10.68.13.228 with SMTP id k4mr1098788pbc.40.1306534223450; Fri, 27 May 2011 15:10:23 -0700 (PDT) Received: from localhost.localdomain ([216.239.45.19]) by mx.google.com with ESMTPS id p5sm812287pbk.84.2011.05.27.15.10.21 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 27 May 2011 15:10:22 -0700 (PDT) From: Kukjin Kim To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/2] ARM: S5P: Add 64bit PWM timer counter for sched_clock Date: Fri, 27 May 2011 15:10:10 -0700 Message-Id: <1306534210-32659-2-git-send-email-kgene.kim@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1306534210-32659-1-git-send-email-kgene.kim@samsung.com> References: <1306534210-32659-1-git-send-email-kgene.kim@samsung.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110527_181025_849526_DD0DCE59 X-CRM114-Status: GOOD ( 21.24 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (kgene.kim[at]gmail.com) 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RFC_ABUSE_POST Both abuse and postmaster missing on sender domain 0.0 T_TO_NO_BRKTS_FREEMAIL T_TO_NO_BRKTS_FREEMAIL Cc: Sangbeom Kim , Kukjin Kim X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 27 May 2011 22:18:06 +0000 (UTC) From: Sangbeom Kim Basically, PWM timer works with 33Mhz on S5P SoCs and counter overflow every 128 secs. So it is needed 64-bit counter for supporting proper sched_clock() by 32-bit timer. This patch handle overflow control and can solve the problem of suspend to resume Signed-off-by: Sangbeom Kim Signed-off-by: Kukjin Kim --- arch/arm/plat-s5p/s5p-time.c | 80 +++++++++++++++++++++++++++++++++++++++-- 1 files changed, 76 insertions(+), 4 deletions(-) diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c index 6b26d80..ecc576f 100644 --- a/arch/arm/plat-s5p/s5p-time.c +++ b/arch/arm/plat-s5p/s5p-time.c @@ -36,6 +36,12 @@ static struct clk *tdiv_source; static struct clk *timerclk; static struct s5p_timer_source timer_source; static unsigned long clock_count_per_tick; +static unsigned long long s5p_sched_timer_overflows; +static unsigned long long time_stamps; +static unsigned long long old_overflows; +static cycle_t last_ticks; +static unsigned int sched_timer_running; +static unsigned int pending_irq; static void s5p_time_setup(enum s5p_timer_mode mode, unsigned long tcnt) { @@ -188,6 +194,7 @@ static void s5p_timer_resume(void) /* source timer restart */ s5p_time_setup(timer_source.source_id, TCNT_MAX); s5p_time_start(timer_source.source_id, PERIODIC); + sched_timer_running = 1; } static cycle_t s5p_timer_read(struct clocksource *cs) @@ -223,6 +230,15 @@ static int s5p_set_next_event(unsigned long cycles, return 0; } +static void s5p_val_init(void) +{ + last_ticks = 0; + s5p_sched_timer_overflows = 0; + old_overflows = 0; + sched_timer_running = 0; + pending_irq = 0; +} + static void s5p_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { @@ -239,6 +255,7 @@ static void s5p_set_mode(enum clock_event_mode mode, case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: + s5p_val_init(); break; case CLOCK_EVT_MODE_RESUME: @@ -322,15 +339,41 @@ static DEFINE_CLOCK_DATA(cd); unsigned long long notrace sched_clock(void) { - cycle_t cyc; + cycle_t ticks, elapsed_ticks = 0; + unsigned long long increment = 0; + unsigned int overflow_cnt = s5p_sched_timer_overflows - old_overflows; unsigned long irq_flags; local_irq_save(irq_flags); - cyc = s5p_timer_read(&time_clocksource); - + ticks = s5p_timer_read(&time_clocksource); + + if (likely(sched_timer_running)) { + if (overflow_cnt) { + increment = (overflow_cnt - 1) + * (clocksource_cyc2ns(time_clocksource.read(&time_clocksource), + time_clocksource.mult, time_clocksource.shift)); + elapsed_ticks = time_clocksource.mask - last_ticks + + ticks; + } else { + if (unlikely(last_ticks > ticks)) { + pending_irq = 1; + elapsed_ticks = time_clocksource.mask + - last_ticks + ticks; + s5p_sched_timer_overflows++; + } else { + elapsed_ticks = ticks - last_ticks; + } + } + + time_stamps += clocksource_cyc2ns(elapsed_ticks, + time_clocksource.mult, time_clocksource.shift) + + increment; + old_overflows = s5p_sched_timer_overflows; + last_ticks = ticks; + } local_irq_restore(irq_flags); - return cyc_to_sched_clock(&cd, cyc, (u32)~0); + return time_stamps; } static void notrace s5p_update_sched_clock(void) @@ -341,10 +384,32 @@ static void notrace s5p_update_sched_clock(void) update_sched_clock(&cd, cyc, (u32)~0); } +irqreturn_t s5p_clock_source_isr(int irq, void *dev_id) +{ + if (unlikely(pending_irq)) + pending_irq = 0; + else + s5p_sched_timer_overflows++; + + return IRQ_HANDLED; +} + +static struct irqaction s5p_clock_source_irq = { + .name = "s5p_source_irq", + .flags = IRQF_DISABLED , + .handler = s5p_clock_source_isr, +}; + static void __init s5p_clocksource_init(void) { unsigned long pclk; unsigned long clock_rate; + unsigned int irq_number; + unsigned long cstat; + + /* Clear each timer interrupt pending bit */ + cstat = __raw_readl(S3C64XX_TINT_CSTAT); + __raw_writel(cstat, S3C64XX_TINT_CSTAT); pclk = clk_get_rate(timerclk); @@ -355,11 +420,15 @@ static void __init s5p_clocksource_init(void) s5p_time_setup(timer_source.source_id, TCNT_MAX); s5p_time_start(timer_source.source_id, PERIODIC); + sched_timer_running = 1; init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate); if (clocksource_register_hz(&time_clocksource, clock_rate)) panic("%s: can't register clocksource\n", time_clocksource.name); + + irq_number = timer_source.source_id + IRQ_TIMER0; + setup_irq(irq_number, &s5p_clock_source_irq); } static void __init s5p_timer_resources(void) @@ -368,6 +437,9 @@ static void __init s5p_timer_resources(void) unsigned long event_id = timer_source.event_id; unsigned long source_id = timer_source.source_id; + s5p_val_init(); + time_stamps = 0; + timerclk = clk_get(NULL, "timers"); if (IS_ERR(timerclk)) panic("failed to get timers clock for timer");