From patchwork Wed Jun 1 09:44:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 839812 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p51CRupF025921 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 1 Jun 2011 12:28:18 GMT Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QRi00-0000RG-77; Wed, 01 Jun 2011 09:46:03 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QRhzy-0001f0-Tk; Wed, 01 Jun 2011 09:45:58 +0000 Received: from opensource.wolfsonmicro.com ([80.75.67.52] helo=opensource2.wolfsonmicro.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QRhz3-0001TB-KQ for linux-arm-kernel@lists.infradead.org; Wed, 01 Jun 2011 09:45:04 +0000 Received: from finisterre.wolfsonmicro.main (unknown [87.246.78.26]) by opensource2.wolfsonmicro.com (Postfix) with ESMTPSA id 7947511493C; Wed, 1 Jun 2011 10:44:59 +0100 (BST) Received: from broonie by finisterre.wolfsonmicro.main with local (Exim 4.76) (envelope-from ) id 1QRhz0-00083G-Qz; Wed, 01 Jun 2011 10:44:58 +0100 From: Mark Brown To: Ben Dooks , Kukjin Kim Subject: [PATCH 3/5] ARM: S3C64XX: Ensure VIC based IRQs can be resumed from Date: Wed, 1 Jun 2011 10:44:51 +0100 Message-Id: <1306921493-30911-3-git-send-email-broonie@opensource.wolfsonmicro.com> X-Mailer: git-send-email 1.7.5.3 In-Reply-To: <1306921493-30911-1-git-send-email-broonie@opensource.wolfsonmicro.com> References: <20110601094313.GA23122@opensource.wolfsonmicro.com> <1306921493-30911-1-git-send-email-broonie@opensource.wolfsonmicro.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110601_054501_972710_87861198 X-CRM114-Status: GOOD ( 16.73 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Mark Brown , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 01 Jun 2011 12:28:18 +0000 (UTC) From: Ben Dooks Any interrupts based off either of the onboard VICs cannot be resumed from any more as it seems set_irq_wake() is now checking the error code returned from the low level handlers and not setting the wake-state on the interrupt if this fails. Ensure that we make the interrupts we can resume from available on the VIC and then do a pre-sleep mask of all the VIC interrupts as the wakeup is handled by a seperate block. Signed-off-by: Ben Dooks Signed-off-by: Mark Brown --- arch/arm/mach-s3c64xx/include/mach/pm-core.h | 2 +- arch/arm/mach-s3c64xx/irq.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index e4f1ce0..38659be 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void) * the IRQ wake controls depending on the CPU we are running on */ #define s3c_irqwake_eintallow ((1 << 28) - 1) -#define s3c_irqwake_intallow (0) +#define s3c_irqwake_intallow (~0) static inline void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c index 97660c8..75d9a0e 100644 --- a/arch/arm/mach-s3c64xx/irq.c +++ b/arch/arm/mach-s3c64xx/irq.c @@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = { }, }; +/* setup the sources the vic should advertise resume for, even though it + * is not doing the wake (set_irq_wake needs to be valid) */ +#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE)) +#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \ + 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \ + 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE)) void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); - vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); + vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); + vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); /* add the timer sub-irqs */ s3c_init_vic_timer_irq(5, IRQ_TIMER0);