From patchwork Fri Jun 3 18:28:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Petr_=C5=A0tetiar?= X-Patchwork-Id: 847992 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p53ISjLt028691 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 3 Jun 2011 18:29:06 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QSZ6l-0006Xl-6W; Fri, 03 Jun 2011 18:28:31 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QSZ6k-0003eF-UB; Fri, 03 Jun 2011 18:28:30 +0000 Received: from ibawizard.net ([82.208.49.253] helo=mengele.ibawizard.net) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QSZ6i-0003dv-04 for linux-arm-kernel@lists.infradead.org; Fri, 03 Jun 2011 18:28:29 +0000 Received: from ntbk.lan (localhost [127.0.0.1]) by mengele.ibawizard.net (Postfix) with ESMTP id 250E31D3612F; Fri, 3 Jun 2011 20:28:15 +0200 (CEST) From: =?UTF-8?q?Petr=20=C5=A0tetiar?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4] ARM: ep93xx: use more reliable CPLD watchdog for reset on ts72xx Date: Fri, 3 Jun 2011 20:28:05 +0200 Message-Id: <1307125685-5110-1-git-send-email-ynezz@true.cz> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110603_142828_227697_AF630FC0 X-CRM114-Status: GOOD ( 13.47 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- Cc: =?UTF-8?q?Petr=20=C5=A0tetiar?= , Ryan Mallon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 03 Jun 2011 18:29:30 +0000 (UTC) X-MIME-Autoconverted: from base64 to 8bit by demeter1.kernel.org id p53ISjLt028691 On all ep93xx based boards from Technologic Systems, there's CPLD watchdog available, so use this one to reset the board instead of the soft reset in CPU. I've seen some weird lockups with the soft reset on ep93xx in the past, while the reset via CPLD watchdog seems to be rock solid (tm) and works fine so far. Cc: Ryan Mallon Acked-by: H Hartley Sweeten Signed-off-by: Petr Štetiar Tested-by: Mika Westerberg --- arch/arm/mach-ep93xx/include/mach/system.h | 18 +++++++++++++----- 1 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index 6d661fe..67ec430 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h @@ -2,7 +2,10 @@ * arch/arm/mach-ep93xx/include/mach/system.h */ +#include + #include +#include static inline void arch_idle(void) { @@ -13,11 +16,16 @@ static inline void arch_reset(char mode, const char *cmd) { local_irq_disable(); - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + if (board_is_ts7200() || board_is_ts7250() || board_is_ts7260() || + board_is_ts7300() || board_is_ts7400()) { + /* We use more reliable CPLD watchdog to perform the reset */ + __raw_writeb(0x5, TS72XX_WDT_FEED_PHYS_BASE); + __raw_writeb(0x1, TS72XX_WDT_CONTROL_PHYS_BASE); + } else { + /* Set then clear the SWRST bit to initiate a software reset */ + ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + } while (1) ;