From patchwork Tue Jun 7 14:22:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 856962 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p57EN7He017688 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 7 Jun 2011 14:23:28 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTxBH-0005mr-Of; Tue, 07 Jun 2011 14:22:56 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QTxBH-0004DM-7A; Tue, 07 Jun 2011 14:22:55 +0000 Received: from mail-iy0-f177.google.com ([209.85.210.177]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTxAw-00049K-Hf for linux-arm-kernel@lists.infradead.org; Tue, 07 Jun 2011 14:22:35 +0000 Received: by iyb39 with SMTP id 39so5581421iyb.36 for ; Tue, 07 Jun 2011 07:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=2KEXr+HEfXDP/un77ynhpju7Swi4XQQBjgH4lKNv/+4=; b=Dpo3ZD3zmEme5X+rgoXv86d0WcSS2IQt/TfMZNik9O/22ymPf/oZ4ccJSvP3CUrDpT jGenzB5Wt+YrSUUR3tAXlWPVxdnCzD+nfimkFURefOqfr/B/Ua3AKucoage1/TakRXV9 LTPgZto/dO+bG9zBuDHPER0FNJN2dqspBm8qk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; b=qDO1OBTZMyyRJtnzeQOuDt/7DgWshKp82PfnMi5VMc6seh94xHyg/O2LAVS2nM255q Fb545KxSpRzm4LluR9dizGK2zt6CI6UP3vlTMrFobE9xj3q1TMR4cTKWZnhqLTiTHm4S RR6fkWNFgjyMEeIGuycTb19dwH1F3cz7JgWtU= Received: by 10.231.116.132 with SMTP id m4mr10024071ibq.86.1307456553281; Tue, 07 Jun 2011 07:22:33 -0700 (PDT) Received: from rob-laptop.i.smooth-stone.com ([173.226.190.126]) by mx.google.com with ESMTPS id s9sm2172964ibe.10.2011.06.07.07.22.32 (version=SSLv3 cipher=OTHER); Tue, 07 Jun 2011 07:22:32 -0700 (PDT) From: Rob Herring To: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] ARM: gic: add OF based initialization Date: Tue, 7 Jun 2011 09:22:20 -0500 Message-Id: <1307456541-11026-3-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1307456541-11026-1-git-send-email-robherring2@gmail.com> References: <1307456541-11026-1-git-send-email-robherring2@gmail.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110607_102234_875639_4566BEB0 X-CRM114-Status: GOOD ( 16.82 ) X-Spam-Score: 1.4 (+) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (robherring2[at]gmail.com) 2.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RFC_ABUSE_POST Both abuse and postmaster missing on sender domain 0.0 T_TO_NO_BRKTS_FREEMAIL T_TO_NO_BRKTS_FREEMAIL X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 07 Jun 2011 14:23:28 +0000 (UTC) From: Rob Herring This adds gic initialization using device tree data. An example device tree binding looks like this: intc: interrupt-controller@fff11000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <1>; interrupt-controller; reg = <0xfff11000 0x1000>, <0xfff10100 0x100>; irq-start = <29>; }; Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/gic.txt | 31 +++++++++++++++++++++ arch/arm/common/gic.c | 36 +++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 3 files changed, 68 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/gic.txt diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt new file mode 100644 index 0000000..491a503 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/gic.txt @@ -0,0 +1,31 @@ +* ARM Generic Interrupt Controller + +Some ARM cores have an interrupt controller called GIC. The ARM GIC +representation in the device tree should be done as under:- + +Required properties: + +- compatible : should be one of: + "arm,cortex-a9-gic" + "arm,arm11mp-gic" + "nvidia,tegra250-gic" +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The type shall be a and the value shall be 1. +- reg : Specifies base physical address(s) and size of the GIC registers. The + first 2 values are the GIC distributor register base and size. The 2nd 2 + values are the GIC cpu interface register base and size. +- irq-start : The first actual interrupt that is connected to h/w. + +Example: + +intc: interrupt-controller@fff11000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xfff11000 0x1000>, + <0xfff10100 0x100>; + irq-start = <29>; +}; + + diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 4ddd0a6..024414d 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -401,3 +403,37 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); } #endif + +#ifdef CONFIG_OF +static struct of_device_id gic_ids[] __initdata = { + { .compatible = "arm,cortex-a9-gic" }, +}; + +void __init gic_of_init(void) +{ + struct device_node *np; + void __iomem *cpu_base; + void __iomem *dist_base; + __u32 irq_start = 16; + const __be32 *val; + + np = of_find_matching_node(NULL, gic_ids); + if (!np) + panic("unable to find compatible gic node in dtb\n"); + + dist_base = of_iomap(np, 0); + if (!dist_base) + panic("unable to map gic dist registers\n"); + + cpu_base = of_iomap(np, 1); + if (!cpu_base) + panic("unable to map gic cpu registers\n"); + + val = of_get_property(np, "irq-start", NULL); + if (val != NULL) + irq_start = of_read_ulong(val, 1); + of_node_put(np); + + gic_init(0, irq_start, dist_base, cpu_base); +} +#endif diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 0691f9d..954a08e 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -37,6 +37,7 @@ extern void __iomem *gic_cpu_base_addr; extern struct irq_chip gic_arch_extn; void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); +void gic_of_init(void); void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);