From patchwork Tue Jun 7 14:22:21 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 856982 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.3) with ESMTP id p57ENipT018464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 7 Jun 2011 14:24:05 GMT Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTxBm-0006NG-R3; Tue, 07 Jun 2011 14:23:27 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QTxBm-0004J1-8r; Tue, 07 Jun 2011 14:23:26 +0000 Received: from mail-iy0-f177.google.com ([209.85.210.177]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QTxAy-0004A4-JH for linux-arm-kernel@lists.infradead.org; Tue, 07 Jun 2011 14:22:38 +0000 Received: by iyb39 with SMTP id 39so5581460iyb.36 for ; Tue, 07 Jun 2011 07:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=G/KGNj9ntshbr9QIO6Xjr9kEOuVZZ/JMpvY+GVjSJKg=; b=pcY32FxQV7g4r3LUcUhaQGgOnCYp8EUgjr1GIGLTbWyP2d/XDZzQJpXigMTrpiFfva Ehhj0TRmgBwbuENOKd1KvaZ//lxbAe8C6tnDYdR619wJsa4US8aX7bmZTVo9j5AVYtBK Ib1zf+E4Wi7E2+T+2xsIsCAd9J+yFC8Uc+vtc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:message-id:x-mailer:in-reply-to:references; b=fAQba4Y6pyT7XKai2fozMNgFSJNc1b0N/O6iUKDBD0zEcnJt07neHkyyshlksQMQ+N uK2WhYT3KF1EueojOenI1ga6Byg983aJwTW4bZW8riOtiRnaJ5SaRxHGOADIn2codtVw jjBh5R8xKqYEBg9qptQ3iETJ89fRUiIGuSAkw= Received: by 10.43.50.9 with SMTP id vc9mr10783617icb.232.1307456555218; Tue, 07 Jun 2011 07:22:35 -0700 (PDT) Received: from rob-laptop.i.smooth-stone.com ([173.226.190.126]) by mx.google.com with ESMTPS id s9sm2172964ibe.10.2011.06.07.07.22.33 (version=SSLv3 cipher=OTHER); Tue, 07 Jun 2011 07:22:33 -0700 (PDT) From: Rob Herring To: devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] ARM: l2x0: Add OF based initialization Date: Tue, 7 Jun 2011 09:22:21 -0500 Message-Id: <1307456541-11026-4-git-send-email-robherring2@gmail.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1307456541-11026-1-git-send-email-robherring2@gmail.com> References: <1307456541-11026-1-git-send-email-robherring2@gmail.com> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110607_102237_004308_C0BC7DC5 X-CRM114-Status: GOOD ( 17.06 ) X-Spam-Score: 1.4 (+) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (1.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (robherring2[at]gmail.com) 2.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (robherring2[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 RFC_ABUSE_POST Both abuse and postmaster missing on sender domain 0.0 T_TO_NO_BRKTS_FREEMAIL T_TO_NO_BRKTS_FREEMAIL X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 07 Jun 2011 14:24:05 +0000 (UTC) From: Rob Herring This adds probing for pl310 cache controller via device tree. An example binding looks like this: L2: l2-cache { compatible = "arm,pl310-cache", "cache"; reg = <0xfff12000 0x1000>; aux-value = <0>; aux-mask = <0xffffffff>; cache-unified; cache-level = <2>; }; Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/l2cc.txt | 35 ++++++++++++++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 38 ++++++++++++++++++++++++ 3 files changed, 74 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/l2cc.txt diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt new file mode 100644 index 0000000..17082be --- /dev/null +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -0,0 +1,35 @@ +* ARM L2 Cache Controller + +ARM cores often have a separate level 2 cache controller. There are various +implementations of the L2 cache controller with compatible programming models. +The ARM L2 cache representation in the device tree should be done as under:- + +Required properties: + +- compatible : should be one of + "arm,pl310-cache" + "arm,l220-cache" + "arm,l210-cache" +- cache-unified : Specifies the cache is a unified cache. +- cache-level : Should be set to 2 for a level 2 cache. +- reg : Physical base address and size of cache controller's memory mapped + registers. + +Optional properties: + +- aux-value : Value to set the Auxillary Control register to. Setting masked + bits is undefined. Default value is 0. +- aux-mask : Mask of bits to preserve in the Auxillary Control register. + Default value is 0xffffffff. + +Example: + +L2: l2-cache { + compatible = "arm,pl310-cache", "cache"; + reg = <0xfff12000 0x1000>; + aux-value = <0>; + aux-mask = <0xffffffff>; + cache-unified; + cache-level = <2>; +}; + diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 16bd480..1d36632 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -74,6 +74,7 @@ #ifndef __ASSEMBLY__ extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern int l2x0_of_init(void); #endif #endif diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ef59099..910f530 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -16,9 +16,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include #include #include #include +#include +#include #include #include @@ -344,3 +347,38 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", ways, cache_id, aux, l2x0_size); } + +#ifdef CONFIG_OF +static struct of_device_id l2x0_ids[] __initdata = { + { .compatible = "arm,pl310-cache" }, + { .compatible = "arm,l220-cache" }, + { .compatible = "arm,l210-cache" }, +}; + +int __init l2x0_of_init(void) +{ + struct device_node *np; + void __iomem *l2_base; + __u32 aux_val = 0; + __u32 aux_mask = ~0UL; + const __be32 *val; + + np = of_find_matching_node(NULL, l2x0_ids); + if (!np) + return -ENODEV; + l2_base = of_iomap(np, 0); + if (!l2_base) + return -ENOMEM; + + val = of_get_property(np, "aux-value", NULL); + if (val != NULL) + aux_val = of_read_ulong(val, 1); + + val = of_get_property(np, "aux-mask", NULL); + if (val != NULL) + aux_mask = of_read_ulong(val, 1); + + l2x0_init(l2_base, aux_val, aux_mask); + return 0; +} +#endif