From patchwork Wed Jun 8 11:23:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindraj.R" X-Patchwork-Id: 862372 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p58JEikg017746 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 8 Jun 2011 19:15:06 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QUGs8-0004BU-92; Wed, 08 Jun 2011 11:24:28 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QUGs7-0001Cp-BX; Wed, 08 Jun 2011 11:24:27 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QUGrM-00013A-21 for linux-arm-kernel@lists.infradead.org; Wed, 08 Jun 2011 11:23:43 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p58BNaPX023190 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 8 Jun 2011 06:23:38 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p58BNZNU012650; Wed, 8 Jun 2011 16:53:35 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Wed, 8 Jun 2011 16:53:35 +0530 Received: from localhost.localdomain (omapldc12.india.ti.com [172.24.136.100]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p58BNT7x028360; Wed, 8 Jun 2011 16:53:34 +0530 (IST) From: "Govindraj.R" To: , , Subject: [PATCH v3 12/12] OMAP4: Serial: Set TX_FIFO_THRESHOLD if uart in dma mode for es2.0 Date: Wed, 8 Jun 2011 16:53:14 +0530 Message-ID: <1307532194-13039-13-git-send-email-govindraj.raja@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1307532194-13039-1-git-send-email-govindraj.raja@ti.com> References: <1307532194-13039-1-git-send-email-govindraj.raja@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110608_072340_581267_810D9A1E X-CRM114-Status: GOOD ( 12.79 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [198.47.26.152 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Tony Lindgren , Kevin Hilman , "Govindraj.R" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 08 Jun 2011 19:15:06 +0000 (UTC) From OMAP4430 ES2.0 onwards if uart is configured in dma mode we need to set uart tx threshold value using the new register UART_TX_DMA_THRESHOLD, this register can used if UART_MDR3 bit(2) is set. We have to ensure tx_threshold + tx_trigger <= 63 from es2.0 onwards. By default we are using tx_trigger of 1 so we can set threshold to 62 to satisfy above criteria. Without the threshold setting we hit dma_sync lost errors on tx channel leading to data loss on rx side Signed-off-by: Govindraj.R --- arch/arm/mach-omap2/serial.c | 4 ++++ arch/arm/plat-omap/include/plat/omap-serial.h | 11 +++++++++++ drivers/tty/serial/omap-serial.c | 5 +++++ 3 files changed, 20 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0a95c95..437fc0b 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -401,6 +401,10 @@ void __init omap_serial_init_port(struct omap_board_data *bdata, if (bdata->id == omap_uart_con_id) pdata->console_uart = true; + if (pdata->dma_enabled && + cpu_is_omap44xx() && omap_rev() > OMAP4430_REV_ES1_0) + pdata->errata |= OMAP4_UART_ERRATA_i659_TX_THR; + od = omap_device_build(name, bdata->id, oh, pdata, sizeof(*pdata), omap_uart_latency, ARRAY_SIZE(omap_uart_latency), false); diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 69e6d4b..0d10f72 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -56,12 +56,23 @@ #define DEFAULT_RXDMA_BUFSIZE 4096 /* RX DMA buffer size */ #define DEFAULT_AUTOSUSPEND_DELAY (30 * HZ) /* Runtime autosuspend (msecs) */ +/* + * (Errata i659) - From OMAP4430 ES 2.0 onwards set + * tx_threshold while using UART in DMA Mode + * and ensure tx_threshold + tx_trigger <= 63 + */ +#define UART_MDR3 0x20 +#define UART_TX_DMA_THRESHOLD 0x21 +#define SET_DMA_TX_THRESHOLD BIT(2) +/* Setting TX Threshold Level to 62 */ +#define TX_FIFO_THR_LVL 0x3E #define OMAP_MAX_HSUART_PORTS 4 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) +#define OMAP4_UART_ERRATA_i659_TX_THR BIT(1) struct omap_uart_port_info { bool dma_enabled; /* To specify DMA Mode */ diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c index dbe76f3..a9645ac 100644 --- a/drivers/tty/serial/omap-serial.c +++ b/drivers/tty/serial/omap-serial.c @@ -818,6 +818,11 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); if (up->use_dma) { + if (up->errata & OMAP4_UART_ERRATA_i659_TX_THR) { + serial_out(up, UART_MDR3, SET_DMA_TX_THRESHOLD); + serial_out(up, UART_TX_DMA_THRESHOLD, TX_FIFO_THR_LVL); + } + serial_out(up, UART_TI752_TLR, 0); serial_out(up, UART_OMAP_SCR, (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8));