From patchwork Sun Jun 12 15:04:56 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Petr_=C5=A0tetiar?= X-Patchwork-Id: 873012 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5CF5tTB013463 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sun, 12 Jun 2011 15:06:17 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QVmEX-0003ar-4Y; Sun, 12 Jun 2011 15:05:49 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QVmEW-0006BA-ML; Sun, 12 Jun 2011 15:05:48 +0000 Received: from ibawizard.net ([82.208.49.253] helo=mengele.ibawizard.net) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QVmES-00069m-DW for linux-arm-kernel@lists.infradead.org; Sun, 12 Jun 2011 15:05:45 +0000 Received: from ntbk.lan (localhost [127.0.0.1]) by mengele.ibawizard.net (Postfix) with ESMTP id 1D5691D3612F; Sun, 12 Jun 2011 17:05:40 +0200 (CEST) From: =?UTF-8?q?Petr=20=C5=A0tetiar?= To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/5] ARM: ep93xx: use more reliable CPLD watchdog for reset on ts72xx Date: Sun, 12 Jun 2011 17:04:56 +0200 Message-Id: <1307891100-31123-2-git-send-email-ynezz@true.cz> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1307891100-31123-1-git-send-email-ynezz@true.cz> References: <1307891100-31123-1-git-send-email-ynezz@true.cz> MIME-Version: 1.0 To: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110612_110544_627640_9FD7745F X-CRM114-Status: GOOD ( 12.92 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- Cc: =?UTF-8?q?Petr=20=C5=A0tetiar?= , Ryan Mallon X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 12 Jun 2011 15:06:17 +0000 (UTC) X-MIME-Autoconverted: from base64 to 8bit by demeter1.kernel.org id p5CF5tTB013463 On all ep93xx based boards from Technologic Systems, there's CPLD watchdog available, so use this one to reset the board instead of the soft reset in CPU. I've seen some weird lockups with the soft reset on ep93xx in the past, while the reset via CPLD watchdog seems to be rock solid (tm) and works fine so far. Cc: Ryan Mallon Tested-by: Mika Westerberg Acked-by: H Hartley Sweeten Signed-off-by: Petr Štetiar --- arch/arm/mach-ep93xx/include/mach/system.h | 18 +++++++++++++----- 1 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index 6d661fe..67ec430 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h @@ -2,7 +2,10 @@ * arch/arm/mach-ep93xx/include/mach/system.h */ +#include + #include +#include static inline void arch_idle(void) { @@ -13,11 +16,16 @@ static inline void arch_reset(char mode, const char *cmd) { local_irq_disable(); - /* - * Set then clear the SWRST bit to initiate a software reset - */ - ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); - ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + if (board_is_ts7200() || board_is_ts7250() || board_is_ts7260() || + board_is_ts7300() || board_is_ts7400()) { + /* We use more reliable CPLD watchdog to perform the reset */ + __raw_writeb(0x5, TS72XX_WDT_FEED_PHYS_BASE); + __raw_writeb(0x1, TS72XX_WDT_CONTROL_PHYS_BASE); + } else { + /* Set then clear the SWRST bit to initiate a software reset */ + ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); + ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); + } while (1) ;