From patchwork Mon Jun 13 00:46:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Cross X-Patchwork-Id: 873722 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p5D0lLfg015294 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 13 Jun 2011 00:47:42 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QVvJD-0006cs-7e; Mon, 13 Jun 2011 00:47:15 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QVvJC-0000sT-Q0; Mon, 13 Jun 2011 00:47:14 +0000 Received: from smtp-out.google.com ([74.125.121.67]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QVvJ9-0000sA-Ds for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2011 00:47:12 +0000 Received: from wpaz13.hot.corp.google.com (wpaz13.hot.corp.google.com [172.24.198.77]) by smtp-out.google.com with ESMTP id p5D0l3DJ003445; Sun, 12 Jun 2011 17:47:03 -0700 Received: from walnut.mtv.corp.google.com (walnut.mtv.corp.google.com [172.18.102.62]) by wpaz13.hot.corp.google.com with ESMTP id p5D0l1ed010063; Sun, 12 Jun 2011 17:47:01 -0700 Received: by walnut.mtv.corp.google.com (Postfix, from userid 99897) id 45AA42576DB; Sun, 12 Jun 2011 17:47:01 -0700 (PDT) From: Colin Cross To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: mm: cache-l2x0: Add support for re-enabling l2x0 Date: Sun, 12 Jun 2011 17:46:58 -0700 Message-Id: <1307926019-28958-1-git-send-email-ccross@android.com> X-Mailer: git-send-email 1.7.4.1 X-System-Of-Record: true X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110612_204711_882225_924B0CCF X-CRM114-Status: GOOD ( 12.27 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [74.125.121.67 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Russell King , Linus Walleij , Tony Lindgren , Catalin Marinas , Sascha Hauer , linux-kernel@vger.kernel.org, Santosh Shilimkar , Colin Cross X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 13 Jun 2011 00:47:42 +0000 (UTC) Remove __init annotation from l2x0_init so it can be used to reinitialize the l2x0 after it has been reset during suspend. Only print the init messages the first time l2x0_init is called. Add l2x0_enable to re-enable the l2x0 after l2x0_disable if the l2x0 was not reset. l2x0_disable cannot use writel, as writel calls wmb(), and wmb() may call outer_cache_sync, which takes the same spinlock as l2x0_disable. Signed-off-by: Colin Cross --- arch/arm/include/asm/hardware/cache-l2x0.h | 3 ++- arch/arm/mm/cache-l2x0.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 16bd480..8fd87fe 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -73,7 +73,8 @@ #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 #ifndef __ASSEMBLY__ -extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); +extern void l2x0_enable(void); #endif #endif diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index ef59099..4db0d9c 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -261,16 +261,26 @@ static void l2x0_flush_range(unsigned long start, unsigned long end) spin_unlock_irqrestore(&l2x0_lock, flags); } +/* enables l2x0 after l2x0_disable, does not invalidate */ +void l2x0_enable(void) +{ + unsigned long flags; + + spin_lock_irqsave(&l2x0_lock, flags); + writel_relaxed(1, l2x0_base + L2X0_CTRL); + spin_unlock_irqrestore(&l2x0_lock, flags); +} + static void l2x0_disable(void) { unsigned long flags; spin_lock_irqsave(&l2x0_lock, flags); - writel(0, l2x0_base + L2X0_CTRL); + writel_relaxed(0, l2x0_base + L2X0_CTRL); spin_unlock_irqrestore(&l2x0_lock, flags); } -void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) +void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) { __u32 aux; __u32 cache_id; @@ -340,7 +350,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.disable = l2x0_disable; outer_cache.set_debug = l2x0_set_debug; - printk(KERN_INFO "%s cache controller enabled\n", type); - printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", + pr_info_once("%s cache controller enabled\n", type); + pr_info_once("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", ways, cache_id, aux, l2x0_size); }