From patchwork Mon Jun 13 11:21:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 874462 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p5DBOR5r024232 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 13 Jun 2011 11:24:48 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QW5Fd-00078h-VO; Mon, 13 Jun 2011 11:24:14 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QW5Fc-0005BB-PP; Mon, 13 Jun 2011 11:24:12 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QW5EM-0004xv-Vp for linux-arm-kernel@canuck.infradead.org; Mon, 13 Jun 2011 11:22:55 +0000 Received: from service87.mimecast.com ([94.185.240.25]) by casper.infradead.org with smtp (Exim 4.76 #1 (Red Hat Linux)) id 1QW5EK-0003pp-Rv for linux-arm-kernel@lists.infradead.org; Mon, 13 Jun 2011 11:22:53 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 13 Jun 2011 12:22:44 +0100 Received: from localhost.localdomain ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 13 Jun 2011 12:22:50 +0100 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v7 03/14] ARM: smp_twd: add support for remapped PPI interrupts Date: Mon, 13 Jun 2011 12:21:48 +0100 Message-Id: <1307964119-4187-4-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1307964119-4187-1-git-send-email-marc.zyngier@arm.com> References: <1307964119-4187-1-git-send-email-marc.zyngier@arm.com> X-OriginalArrivalTime: 13 Jun 2011 11:22:50.0700 (UTC) FILETIME=[3AFAB0C0:01CC29BC] X-MC-Unique: 111061312224402401 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110613_122253_003028_F591417C X-CRM114-Status: GOOD ( 14.39 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2-r929478 on casper.infradead.org summary: Content analysis details: (-2.6 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [94.185.240.25 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Thomas Gleixner X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 13 Jun 2011 11:24:48 +0000 (UTC) When CONFIG_ARM_GIC_VPPI is enabled, let smp_twd request interrupts the normal way (ie using request_irq()). This involves letting PPIs go via the same code path as SPIs and having normal interrupt handler for the local timer code. The previous ad-hoc code is still supported when CONFIG_ARM_GIC_VPPI is not defined. Signed-off-by: Marc Zyngier Reviewed-by: Will Deacon --- arch/arm/kernel/smp_twd.c | 28 +++++++++++++++++++++++++++- 1 files changed, 27 insertions(+), 1 deletions(-) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 60636f4..773336e 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -15,16 +15,18 @@ #include #include #include -#include +#include #include #include +#include #include /* set up by the platform code */ void __iomem *twd_base; static unsigned long twd_timer_rate; +static DEFINE_PER_CPU(bool, irq_reqd); static void twd_set_mode(enum clock_event_mode mode, struct clock_event_device *clk) @@ -43,6 +45,10 @@ static void twd_set_mode(enum clock_event_mode mode, ctrl = TWD_TIMER_CONTROL_IT_ENABLE | TWD_TIMER_CONTROL_ONESHOT; break; case CLOCK_EVT_MODE_UNUSED: +#ifdef CONFIG_ARM_GIC_VPPI + disable_irq(clk->irq); + /* fall through */ +#endif case CLOCK_EVT_MODE_SHUTDOWN: default: ctrl = 0; @@ -124,6 +130,9 @@ static void __cpuinit twd_calibrate_rate(void) */ void __cpuinit twd_timer_setup(struct clock_event_device *clk) { + int err; + bool *reqd; + twd_calibrate_rate(); clk->name = "local_timer"; @@ -137,8 +146,25 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); clk->min_delta_ns = clockevent_delta2ns(0xf, clk); +#ifdef CONFIG_ARM_GIC_VPPI + reqd = &__get_cpu_var(irq_reqd); + if (!*reqd) { + err = request_irq(clk->irq, percpu_timer_handler, + IRQF_PERCPU | IRQF_NOBALANCING | IRQF_TIMER, + clk->name, clk); + if (err) { + pr_err("%s: can't register interrupt %d on cpu %d (%d)\n", + clk->name, clk->irq, smp_processor_id(), err); + return; + } + + *reqd = true; + } else + enable_irq(clk->irq); +#else /* Make sure our local interrupt controller has this enabled */ gic_enable_ppi(clk->irq); +#endif clockevents_register_device(clk); }