From patchwork Mon Jun 20 13:37:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 897352 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5KDX5oA019152 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 20 Jun 2011 13:33:25 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYeah-0003KA-CK; Mon, 20 Jun 2011 13:32:36 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QYeag-0001Rw-UN; Mon, 20 Jun 2011 13:32:34 +0000 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16] helo=VA3EHSOBE007.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYeaO-0001Ok-3W for linux-arm-kernel@lists.infradead.org; Mon, 20 Jun 2011 13:32:17 +0000 Received: from mail25-va3-R.bigfish.com (10.7.14.238) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.22; Mon, 20 Jun 2011 13:32:14 +0000 Received: from mail25-va3 (localhost.localdomain [127.0.0.1]) by mail25-va3-R.bigfish.com (Postfix) with ESMTP id 1E655B18258; Mon, 20 Jun 2011 13:32:14 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail25-va3 (localhost.localdomain [127.0.0.1]) by mail25-va3 (MessageSwitch) id 1308576693120067_5933; Mon, 20 Jun 2011 13:31:33 +0000 (UTC) Received: from VA3EHSMHS011.bigfish.com (unknown [10.7.14.246]) by mail25-va3.bigfish.com (Postfix) with ESMTP id 5E27029014E; Mon, 20 Jun 2011 13:30:31 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS011.bigfish.com (10.7.99.21) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 20 Jun 2011 13:30:29 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Mon, 20 Jun 2011 08:30:29 -0500 Received: from localhost.localdomain ([10.29.240.182]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p5KDURaJ016841; Mon, 20 Jun 2011 08:30:28 -0500 (CDT) From: Fabio Estevam To: Subject: [PATCH v2] ARM: mach-imx/mx31_3ds: Fix IOMUX for SPI1 signals Date: Mon, 20 Jun 2011 10:37:13 -0300 Message-ID: <1308577033-10678-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.6.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110620_093216_320059_C86C5732 X-CRM114-Status: GOOD ( 19.61 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.32.180.16 listed in list.dnswl.org] Cc: Fabio Estevam , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 20 Jun 2011 13:33:26 +0000 (UTC) Original code was assuming that the CSPI1 pins on the MX31PDK were the primary pin function, which is incorrect. On MX31PDK board these are the pins that provide CSPI1 functionality: DSR_DCE1 (ALT mode 1) --> CSPI1_CLK RI_DCE1 (ALT mode 1) --> CSPI1_RDY DTR_DTE1 -->CSI1_MOSI DSR_DTE1 --> CSPI1_MISO DTR_DCE2 ---> CSPI1_SS2 The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM. This patch fixes the CSPI1 IOMUX and makes the LCD to be functional. Signed-off-by: Fabio Estevam --- Changes since v1: - Provided better explanation about this change on the commit message arch/arm/mach-imx/mach-mx31_3ds.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index ab2a626..a6160ee 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c @@ -53,11 +53,8 @@ static int mx31_3ds_pins[] = { MX31_PIN_RXD1__RXD1, IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /*SPI0*/ - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */ + IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), + IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), /* SPI 1 */ MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_MOSI__MOSI, @@ -690,6 +687,9 @@ static void __init mx31_3ds_init(void) int ret; imx31_soc_init(); + + /* Configure SPI1 IOMUX */ + mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), "mx31_3ds");