From patchwork Mon Jun 20 13:40:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 897422 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p5KDgQwR020733 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 20 Jun 2011 13:42:47 GMT Received: from canuck.infradead.org ([134.117.69.58]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYejd-0004oU-Pk; Mon, 20 Jun 2011 13:41:51 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QYejd-0001n6-CJ; Mon, 20 Jun 2011 13:41:49 +0000 Received: from mail-ww0-f41.google.com ([74.125.82.41]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYeia-0001Y8-Qe for linux-arm-kernel@lists.infradead.org; Mon, 20 Jun 2011 13:40:46 +0000 Received: by wwi18 with SMTP id 18so2617174wwi.0 for ; Mon, 20 Jun 2011 06:40:41 -0700 (PDT) Received: by 10.227.32.73 with SMTP id b9mr4928566wbd.86.1308577241760; Mon, 20 Jun 2011 06:40:41 -0700 (PDT) Received: from e200948.peterhouse.linaro.org (fw-lnat.cambridge.arm.com [217.140.96.63]) by mx.google.com with ESMTPS id fr17sm2359178wbb.40.2011.06.20.06.40.40 (version=SSLv3 cipher=OTHER); Mon, 20 Jun 2011 06:40:41 -0700 (PDT) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] ARM: Documentation: clarify entry requirements for ARM versus Thumb-2 Date: Mon, 20 Jun 2011 14:40:29 +0100 Message-Id: <1308577229-23681-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1308577229-23681-1-git-send-email-dave.martin@linaro.org> References: <1308577229-23681-1-git-send-email-dave.martin@linaro.org> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110620_094045_073741_76FD5B60 X-CRM114-Status: GOOD ( 14.52 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.82.41 listed in list.dnswl.org] Cc: Nicolas Pitre , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 20 Jun 2011 13:42:48 +0000 (UTC) Currently, the kernel entry requirements are not explicit about whether the kernel should be entered in ARM or Thumb-2. Now that the boot protocol consistently requires the kernel Image or zImage to be entered in ARM state, document this requirement explicitly. A different rule will be needed for Cortex-M class CPUs as and when support for these lands upstream, since these CPUs don't support the ARM instruction set at all: a note is added to the effect that the kernel must be entered in Thumb on such systems. Signed-off-by: Dave Martin --- Documentation/arm/Booting | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting index 4e686a2..a341d87 100644 --- a/Documentation/arm/Booting +++ b/Documentation/arm/Booting @@ -164,3 +164,8 @@ In either case, the following conditions must be met: - The boot loader is expected to call the kernel image by jumping directly to the first instruction of the kernel image. + On CPUs supporting the ARM instruction set, the entry must be + made in ARM state, even for a Thumb-2 kernel. + + On CPUs supporting only the Thumb instruction set such as + Cortex-M class CPUs, the entry must be made in Thumb state.