From patchwork Tue Jun 21 05:32:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 899812 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p5L5dGjQ025299 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 21 Jun 2011 05:39:37 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYtg3-0004E8-Bd; Tue, 21 Jun 2011 05:39:07 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QYtg3-0006jz-0R; Tue, 21 Jun 2011 05:39:07 +0000 Received: from mail-vw0-f49.google.com ([209.85.212.49]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QYtfw-0006jg-0j for linux-arm-kernel@lists.infradead.org; Tue, 21 Jun 2011 05:39:04 +0000 Received: by vws8 with SMTP id 8so3634009vws.36 for ; Mon, 20 Jun 2011 22:38:58 -0700 (PDT) Received: by 10.52.180.135 with SMTP id do7mr2386439vdc.273.1308634410310; Mon, 20 Jun 2011 22:33:30 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id t13sm2033281vds.30.2011.06.20.22.33.27 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Jun 2011 22:33:29 -0700 (PDT) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: EXYNOS4: Suspend to RAM fix Date: Tue, 21 Jun 2011 11:02:31 +0530 Message-Id: <1308634351-8511-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.1 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110621_013900_142940_5DD783C1 X-CRM114-Status: GOOD ( 14.87 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.49 listed in list.dnswl.org] Cc: kgene.kim@samsung.com, samsung@lists.linaro.org, inderpal.s@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 21 Jun 2011 05:39:37 +0000 (UTC) From: Inderpal Singh This patch caters to the case when there is no wake up source. The system should abort the suspend and resume properly. 1. It implements the pm_suspend function to save the core registers so that they can be restored in pm_resume function. Earlier these resgisters were getting saved in pm_prepare, but pm_prepare never gets invoked when there is no wake up source enabled and restoration used to hang while resuming. 2. As per the L2 cache controller spec, the cache controller registers should not be modified if cache is already enabled. Hence have made restoration of cache controller registers conditional based on whether it is already enabled or not. Signed-off-by: Inderpal Singh --- arch/arm/mach-exynos4/pm.c | 22 +++++++++++++++++----- 1 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 8755ca8..f483dae 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -324,8 +324,9 @@ static void exynos4_pm_prepare(void) { u32 tmp; - s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); +#ifdef CONFIG_CACHE_L2X0 s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); +#endif tmp = __raw_readl(S5P_INFORM1); @@ -410,15 +411,26 @@ static void exynos4_pm_resume(void) exynos4_scu_enable(S5P_VA_SCU); #ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); + /* Restore the cache controller registers only if it is not enabled already*/ + if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL)&1)) { + + s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); + outer_inv_all(); + /* enable L2X0*/ + writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); + } #endif } +static int exynos4_pm_suspend(void) +{ + s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); + return 0; +} + static struct syscore_ops exynos4_pm_syscore_ops = { .resume = exynos4_pm_resume, + .suspend = exynos4_pm_suspend, }; static __init int exynos4_pm_syscore_init(void)