diff mbox

[2/2] ARM: pxa168: correct nand pmu setting

Message ID 1308650059-27226-2-git-send-email-leiwen@marvell.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lei Wen June 21, 2011, 9:54 a.m. UTC
The original pair of <0x01db, 208000000> is invalid.
Correct to the valid value.

Signed-off-by: Lei Wen <leiwen@marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Eric Miao June 21, 2011, 10:09 a.m. UTC | #1
On Tue, Jun 21, 2011 at 5:54 PM, Lei Wen <leiwen@marvell.com> wrote:
> The original pair of <0x01db, 208000000> is invalid.
> Correct to the valid value.
>
> Signed-off-by: Lei Wen <leiwen@marvell.com>

Lei,

As pxa168 boards are available outside now, please describe more on this
change. Due to silicon revision, erratum, or due to the original code was
too long ago that it is no long valid.

Note - check the pxa168 boards file, make sure the change will not affect
them.

> ---
>  arch/arm/mach-mmp/pxa168.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
> index 72b4e76..ab9f999 100644
> --- a/arch/arm/mach-mmp/pxa168.c
> +++ b/arch/arm/mach-mmp/pxa168.c
> @@ -79,7 +79,7 @@ static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
>  static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
>  static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
>
> -static APMU_CLK(nand, NAND, 0x01db, 208000000);
> +static APMU_CLK(nand, NAND, 0x19b, 156000000);
>  static APMU_CLK(lcd, LCD, 0x7f, 312000000);
>
>  /* device and clock bindings */
> --
> 1.7.0.4
>
>
Lei Wen June 21, 2011, 10:14 a.m. UTC | #2
Hi Eric,

On Tue, Jun 21, 2011 at 6:09 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
> On Tue, Jun 21, 2011 at 5:54 PM, Lei Wen <leiwen@marvell.com> wrote:
>> The original pair of <0x01db, 208000000> is invalid.
>> Correct to the valid value.
>>
>> Signed-off-by: Lei Wen <leiwen@marvell.com>
>
> Lei,
>
> As pxa168 boards are available outside now, please describe more on this
> change. Due to silicon revision, erratum, or due to the original code was
> too long ago that it is no long valid.
>
> Note - check the pxa168 boards file, make sure the change will not affect
> them.

That value 0x01db only means 78Mhz, and from all doc I could refer to
the 0x01db never reach
to 208MHZ...

Do you means I should keep the 0x1db register value?

Thanks,
Lei
Eric Miao June 21, 2011, 10:17 a.m. UTC | #3
On Tue, Jun 21, 2011 at 6:14 PM, Lei Wen <adrian.wenl@gmail.com> wrote:
> Hi Eric,
>
> On Tue, Jun 21, 2011 at 6:09 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
>> On Tue, Jun 21, 2011 at 5:54 PM, Lei Wen <leiwen@marvell.com> wrote:
>>> The original pair of <0x01db, 208000000> is invalid.
>>> Correct to the valid value.
>>>
>>> Signed-off-by: Lei Wen <leiwen@marvell.com>
>>
>> Lei,
>>
>> As pxa168 boards are available outside now, please describe more on this
>> change. Due to silicon revision, erratum, or due to the original code was
>> too long ago that it is no long valid.
>>
>> Note - check the pxa168 boards file, make sure the change will not affect
>> them.
>
> That value 0x01db only means 78Mhz, and from all doc I could refer to
> the 0x01db never reach
> to 208MHZ...
>
> Do you means I should keep the 0x1db register value?

I didn't mean that. I just want to make it clear why the original code was
wrong. So my understanding:

1. 0x01db was wrong - it doesn't make a clock rate of 208MHz
2. 208MHz was also wrong - the default should be 156MHz?

Am I right on this?
Lei Wen June 21, 2011, 10:21 a.m. UTC | #4
On Tue, Jun 21, 2011 at 6:17 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
> On Tue, Jun 21, 2011 at 6:14 PM, Lei Wen <adrian.wenl@gmail.com> wrote:
>> Hi Eric,
>>
>> On Tue, Jun 21, 2011 at 6:09 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
>>> On Tue, Jun 21, 2011 at 5:54 PM, Lei Wen <leiwen@marvell.com> wrote:
>>>> The original pair of <0x01db, 208000000> is invalid.
>>>> Correct to the valid value.
>>>>
>>>> Signed-off-by: Lei Wen <leiwen@marvell.com>
>>>
>>> Lei,
>>>
>>> As pxa168 boards are available outside now, please describe more on this
>>> change. Due to silicon revision, erratum, or due to the original code was
>>> too long ago that it is no long valid.
>>>
>>> Note - check the pxa168 boards file, make sure the change will not affect
>>> them.
>>
>> That value 0x01db only means 78Mhz, and from all doc I could refer to
>> the 0x01db never reach
>> to 208MHZ...
>>
>> Do you means I should keep the 0x1db register value?
>
> I didn't mean that. I just want to make it clear why the original code was
> wrong. So my understanding:
>
> 1. 0x01db was wrong - it doesn't make a clock rate of 208MHz
0x1db is valid value, and yes it doesn't make a clock rate to 208Mhz,
but only to 78Mhz

> 2. 208MHz was also wrong - the default should be 156MHz?
208Mhz is totally wrong, the NFC never reach this on pxa168.

So the 0x1db<->78Mhz, and 0x19b<->156Mhz.

Best regards,
Lei
Eric Miao June 21, 2011, 10:25 a.m. UTC | #5
On Tue, Jun 21, 2011 at 6:21 PM, Lei Wen <adrian.wenl@gmail.com> wrote:
> On Tue, Jun 21, 2011 at 6:17 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
>> On Tue, Jun 21, 2011 at 6:14 PM, Lei Wen <adrian.wenl@gmail.com> wrote:
>>> Hi Eric,
>>>
>>> On Tue, Jun 21, 2011 at 6:09 PM, Eric Miao <eric.y.miao@gmail.com> wrote:
>>>> On Tue, Jun 21, 2011 at 5:54 PM, Lei Wen <leiwen@marvell.com> wrote:
>>>>> The original pair of <0x01db, 208000000> is invalid.
>>>>> Correct to the valid value.
>>>>>
>>>>> Signed-off-by: Lei Wen <leiwen@marvell.com>
>>>>
>>>> Lei,
>>>>
>>>> As pxa168 boards are available outside now, please describe more on this
>>>> change. Due to silicon revision, erratum, or due to the original code was
>>>> too long ago that it is no long valid.
>>>>
>>>> Note - check the pxa168 boards file, make sure the change will not affect
>>>> them.
>>>
>>> That value 0x01db only means 78Mhz, and from all doc I could refer to
>>> the 0x01db never reach
>>> to 208MHZ...
>>>
>>> Do you means I should keep the 0x1db register value?
>>
>> I didn't mean that. I just want to make it clear why the original code was
>> wrong. So my understanding:
>>
>> 1. 0x01db was wrong - it doesn't make a clock rate of 208MHz
> 0x1db is valid value, and yes it doesn't make a clock rate to 208Mhz,
> but only to 78Mhz
>
>> 2. 208MHz was also wrong - the default should be 156MHz?
> 208Mhz is totally wrong, the NFC never reach this on pxa168.
>
> So the 0x1db<->78Mhz, and 0x19b<->156Mhz.
>

OK, that makes a lot sense. Could you update the patch with the
above description in the commit message? Thanks.

> Best regards,
> Lei
>
diff mbox

Patch

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 72b4e76..ab9f999 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -79,7 +79,7 @@  static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 
-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(lcd, LCD, 0x7f, 312000000);
 
 /* device and clock bindings */