From patchwork Fri Jul 1 21:54:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 938502 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p61LtFOE009034 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 1 Jul 2011 21:55:36 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qclfw-0005qC-Bv; Fri, 01 Jul 2011 21:55:00 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qclfw-0001dx-0o; Fri, 01 Jul 2011 21:55:00 +0000 Received: from arroyo.ext.ti.com ([192.94.94.40]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QclfY-0001a5-7c for linux-arm-kernel@lists.infradead.org; Fri, 01 Jul 2011 21:54:37 +0000 Received: from dlep36.itg.ti.com ([157.170.170.91]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id p61LsYrY027154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 1 Jul 2011 16:54:34 -0500 Received: from dlep26.itg.ti.com (smtp-le.itg.ti.com [157.170.170.27]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id p61LsYKm005024; Fri, 1 Jul 2011 16:54:34 -0500 (CDT) Received: from dlee73.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id p61LsYi5000821; Fri, 1 Jul 2011 16:54:34 -0500 (CDT) Received: from dlelxv22.itg.ti.com (172.17.1.197) by DLEE73.ent.ti.com (157.170.170.88) with Microsoft SMTP Server id 8.3.106.1; Fri, 1 Jul 2011 16:54:34 -0500 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id p61LsUJV024787; Fri, 1 Jul 2011 16:54:32 -0500 From: Benoit Cousson To: Subject: [PATCH v2 1/4] OMAP4: hwmod data: Add GPMC Date: Fri, 1 Jul 2011 23:54:24 +0200 Message-ID: <1309557267-27165-2-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1309557267-27165-1-git-send-email-b-cousson@ti.com> References: <1309557267-27165-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110701_175436_419156_75FDA98E X-CRM114-Status: GOOD ( 18.23 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.40 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Kevin Hilman , linux-omap@vger.kernel.org, rnayak@ti.com, Benoit Cousson , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Fri, 01 Jul 2011 21:55:36 +0000 (UTC) Add the GPMC hwmod data. The GPMC hwmod does need the flags HWMOD_INIT_NO_IDLE and HWMOD_INIT_NO_RESET due to a bug described in the previous commit: OMAP4: clock: Keep GPMC clocks always enabled and hardware managed On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. Because of CPU speculative nature, such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. Above makes access to GPMC unpredictable during the execution, so it's module mode needs to be kept under hardware control instead of software control. Since the auto gating is supported for GPMC, there isn't any power impact because of this change. The issue was un-covered with security middleware running along with HLOS. In this case GPMC had a valid MMU descriptor on secure side where as HLOS didn't map the GMPC because it isn't being used. Signed-off-by: Benoit Cousson Cc: Kevin Hilman Cc: Paul Walmsley Cc: Rajendra Nayak --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 78 +++++++++++++++++++++++++++- 1 files changed, 77 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 160c77a..e2971bc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -701,7 +701,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = { * emif1 * emif2 * fdif - * gpmc * gpu * hdq1w * mcasp @@ -2195,6 +2194,80 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { }; /* + * 'gpmc' class + * general purpose memory controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &omap44xx_gpmc_sysc, +}; + +/* gpmc */ +static struct omap_hwmod omap44xx_gpmc_hwmod; +static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { + { .irq = 20 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { + { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x500003ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_2 -> gpmc */ +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { + .master = &omap44xx_l3_main_2_hwmod, + .slave = &omap44xx_gpmc_hwmod, + .clk = "l3_div_ck", + .addr = omap44xx_gpmc_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_gpmc_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* gpmc slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_gpmc_slaves[] = { + &omap44xx_l3_main_2__gpmc, +}; + +static struct omap_hwmod omap44xx_gpmc_hwmod = { + .name = "gpmc", + .class = &omap44xx_gpmc_hwmod_class, + .clkdm_name = "l3_2_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_gpmc_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpmc_irqs), + .sdma_reqs = omap44xx_gpmc_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_gpmc_sdma_reqs), + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, + .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .slaves = omap44xx_gpmc_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_gpmc_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP44XX), +}; + +/* * 'hsi' class * mipi high-speed synchronous serial interface (multichannel and full-duplex * serial if) @@ -5392,6 +5465,9 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_gpio5_hwmod, &omap44xx_gpio6_hwmod, + /* gpmc class */ + &omap44xx_gpmc_hwmod, + /* hsi class */ /* &omap44xx_hsi_hwmod, */