From patchwork Tue Jul 5 15:19:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 945662 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p65FDqUq017567 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 5 Jul 2011 15:14:13 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qe7Jb-0004vW-Hy; Tue, 05 Jul 2011 15:13:31 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qe7Ja-0004V5-Ve; Tue, 05 Jul 2011 15:13:30 +0000 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16] helo=VA3EHSOBE007.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qe7JJ-0004S7-LU for linux-arm-kernel@lists.infradead.org; Tue, 05 Jul 2011 15:13:15 +0000 Received: from mail77-va3-R.bigfish.com (10.7.14.245) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.22; Tue, 5 Jul 2011 15:13:10 +0000 Received: from mail77-va3 (localhost.localdomain [127.0.0.1]) by mail77-va3-R.bigfish.com (Postfix) with ESMTP id BFD4F1A181BE; Tue, 5 Jul 2011 15:13:10 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275dhz2dh87h2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-FB-DOMAIN-IP-MATCH: fail Received: from mail77-va3 (localhost.localdomain [127.0.0.1]) by mail77-va3 (MessageSwitch) id 1309878790395724_12128; Tue, 5 Jul 2011 15:13:10 +0000 (UTC) Received: from VA3EHSMHS001.bigfish.com (unknown [10.7.14.244]) by mail77-va3.bigfish.com (Postfix) with ESMTP id 4FD8F560052; Tue, 5 Jul 2011 15:13:10 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS001.bigfish.com (10.7.99.11) with Microsoft SMTP Server (TLS) id 14.1.225.22; Tue, 5 Jul 2011 15:13:06 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server id 14.1.289.8; Tue, 5 Jul 2011 10:13:05 -0500 Received: from S2100-06.ap.freescale.net (S2100-06.ap.freescale.net [10.192.242.125]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p65FD0QB011592; Tue, 5 Jul 2011 10:13:03 -0500 (CDT) From: Shawn Guo To: Subject: [PATCH v2 1/3] gpio/mxc: get gpio range/base from gpio core Date: Tue, 5 Jul 2011 23:19:24 +0800 Message-ID: <1309879166-25788-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1309879166-25788-1-git-send-email-shawn.guo@linaro.org> References: <1309879166-25788-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110705_111314_085639_340FD4E9 X-CRM114-Status: GOOD ( 24.25 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.32.180.16 listed in list.dnswl.org] Cc: Grant Likely , devicetree-discuss@lists.ozlabs.org, Shawn Guo , Sascha Hauer , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Tue, 05 Jul 2011 15:14:13 +0000 (UTC) Instead of assigning the gpio range based on pdev->id, the patch makes changes to get the range from gpio core that is dynamically allocated. As a result, the uses of pdev->id can be removed from the driver. This will make dt migration of the driver easier. Signed-off-by: Shawn Guo Cc: Grant Likely Cc: Sascha Hauer --- arch/arm/plat-mxc/include/mach/gpio.h | 13 +++++++++---- arch/arm/plat-mxc/include/mach/irqs.h | 21 +++------------------ drivers/gpio/gpio-mxc.c | 18 ++++++++++-------- 3 files changed, 22 insertions(+), 30 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h index 31c820c..abdf5d7 100644 --- a/arch/arm/plat-mxc/include/mach/gpio.h +++ b/arch/arm/plat-mxc/include/mach/gpio.h @@ -23,10 +23,15 @@ #include #include - -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) +/* + * There's a off-by-one betweem the gpio bank number and the gpiochip + * range e.g. GPIO_1_5 is gpio 5 under linux. + * + * When gpio core allocates gpio range for a bank, it starts from the + * end of the total range. That is to say, bank 0 will get a higher + * gpio range than bank 1. + */ +#define IMX_GPIO_NR(bank, nr) (ARCH_NR_GPIOS - (bank) * 32 + (nr)) /* use gpiolib dispatchers */ #define gpio_get_value __gpio_get_value diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 35c89bc..00e812b 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_MXC_IRQS_H__ #define __ASM_ARCH_MXC_IRQS_H__ +#include + /* * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ @@ -22,30 +24,13 @@ #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -/* these are ordered by size to support multi-SoC kernels */ -#if defined CONFIG_SOC_IMX53 -#define MXC_GPIO_IRQS (32 * 7) -#elif defined CONFIG_ARCH_MX2 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_SOC_IMX50 -#define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX25 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_SOC_IMX51 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use * these. If you need more, increase MXC_BOARD_IRQS, but keep it * within sensible limits. */ -#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS) +#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS) #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #define MXC_BOARD_IRQS 80 diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 2f6a81b..8241680 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -240,14 +240,13 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev) { struct mxc_gpio_port *port; struct resource *iores; + static int once = 0; int err; port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL); if (!port) return -ENOMEM; - port->virtual_irq_start = MXC_GPIO_IRQ_START + pdev->id * 32; - iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!iores) { err = -ENODEV; @@ -277,14 +276,13 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev) writel(0, port->base + GPIO_IMR); writel(~0, port->base + GPIO_ISR); - /* gpio-mxc can be a generic irq chip */ - mxc_gpio_init_gc(port); - if (cpu_is_mx2()) { /* setup one handler for all GPIO interrupts */ - if (pdev->id == 0) + if (!once) { irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); + once = 1; + } } else { /* setup one handler for each entry */ irq_set_chained_handler(port->irq, mx3_gpio_irq_handler); @@ -304,12 +302,16 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev) if (err) goto out_iounmap; - port->bgc.gc.base = pdev->id * 32; - err = gpiochip_add(&port->bgc.gc); if (err) goto out_bgpio_remove; + /* Here, we get a gpio number range/base assigned by gpio core */ + port->virtual_irq_start = MXC_GPIO_IRQ_START + port->bgc.gc.base; + + /* gpio-mxc can be a generic irq chip */ + mxc_gpio_init_gc(port); + list_add_tail(&port->node, &mxc_gpio_ports); return 0;