From patchwork Mon Jul 11 11:21:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 964682 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6BCsGnl014307 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 11 Jul 2011 12:54:38 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgFzs-0007iK-6t; Mon, 11 Jul 2011 12:54:01 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QgFzn-0004MX-Ia; Mon, 11 Jul 2011 12:53:55 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgFv1-00035t-OJ for linux-arm-kernel@lists.infradead.org; Mon, 11 Jul 2011 12:49:04 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6BCmtAW014959 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 11 Jul 2011 07:48:57 -0500 Received: from dbde70.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6BCmTxo013053; Mon, 11 Jul 2011 18:18:54 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com (172.24.170.148) with Microsoft SMTP Server id 8.3.106.1; Mon, 11 Jul 2011 16:52:00 +0530 Received: from localhost.localdomain ([172.24.190.106]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6BBLap7020454; Mon, 11 Jul 2011 16:51:57 +0530 (IST) From: Tarun Kanti DebBarma To: Subject: [PATCH v14 08/12] OMAP: dmtimer: add timeout to low-level routines Date: Mon, 11 Jul 2011 16:51:32 +0530 Message-ID: <1310383296-18956-9-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1310383296-18956-1-git-send-email-tarun.kanti@ti.com> References: <1310383296-18956-1-git-send-email-tarun.kanti@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110711_084900_148076_E2B5CBDC X-CRM114-Status: GOOD ( 11.71 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [192.94.94.41 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, tony@atomide.com, santosh.shilimkar@ti.com, Tarun Kanti DebBarma , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 11 Jul 2011 12:54:38 +0000 (UTC) The low-level read and write access routines wait on write-pending register in posted mode to make sure that previous write is complete on respective registers. This waiting is done in an infinite while loop. Now it is being modified to use timeout instead. Signed-off-by: Tarun Kanti DebBarma Reviewed-by: Varadarajan, Charulatha Acked-by: Cousson, Benoit --- arch/arm/plat-omap/include/plat/dmtimer.h | 34 ++++++++++++++++++++-------- 1 files changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 53d5da6..6e34094 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -36,6 +36,8 @@ #include #include +#include + #ifndef __ASM_ARCH_DMTIMER_H #define __ASM_ARCH_DMTIMER_H @@ -230,6 +232,8 @@ int omap_dm_timers_active(void); #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) +#define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */ + struct omap_dm_timer { unsigned long phys_base; int id; @@ -251,11 +255,16 @@ void omap_dm_timer_prepare(struct omap_dm_timer *timer); static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, int posted, u8 func_offset) { - if (posted) - while (__raw_readl(base + - ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + int i = 0; + + if (posted) { + omap_test_timeout(!(__raw_readl(base + + ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) & + (reg >> WPSHIFT)), MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT)) + pr_err("read timeout.\n"); + } return __raw_readl(base + (reg & 0xff)); } @@ -263,11 +272,16 @@ static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val, int posted, u8 func_offset) { - if (posted) - while (__raw_readl(base + - ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + int i = 0; + + if (posted) { + omap_test_timeout(!(__raw_readl(base + + ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) & + (reg >> WPSHIFT)), MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON(i == MAX_WRITE_PEND_WAIT)) + pr_err("write timeout.\n"); + } __raw_writel(val, base + (reg & 0xff)); }