From patchwork Wed Jul 13 13:54:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 972192 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p6DE1sTP010925 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 13 Jul 2011 14:02:15 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QgzzY-0001YV-V9; Wed, 13 Jul 2011 14:00:46 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QgzzY-0002pT-DG; Wed, 13 Jul 2011 14:00:44 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qgzu9-0001Ij-Rs for linux-arm-kernel@lists.infradead.org; Wed, 13 Jul 2011 13:55:14 +0000 Received: from dbdp20.itg.ti.com ([172.24.170.38]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p6DDt58h029053 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 13 Jul 2011 08:55:08 -0500 Received: from dbde71.ent.ti.com (localhost [127.0.0.1]) by dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6DDt5ww001782; Wed, 13 Jul 2011 19:25:05 +0530 (IST) Received: from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com (172.24.170.149) with Microsoft SMTP Server id 8.3.106.1; Wed, 13 Jul 2011 19:25:05 +0530 Received: from localhost.localdomain ([172.24.190.106]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p6DDsKD4020505; Wed, 13 Jul 2011 19:25:02 +0530 (IST) From: Tarun Kanti DebBarma To: Subject: [PATCH v4 20/20] gpio/omap: cleanup prepare_for_idle and resume_after_idle Date: Wed, 13 Jul 2011 19:24:19 +0530 Message-ID: <1310565259-31267-21-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1310565259-31267-1-git-send-email-tarun.kanti@ti.com> References: <1310565259-31267-1-git-send-email-tarun.kanti@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110713_095510_208625_A73DB6C9 X-CRM114-Status: GOOD ( 17.64 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [198.47.26.152 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: khilman@ti.com, tony@atomide.com, santosh.shilimkar@ti.com, Tarun Kanti DebBarma , linux-arm-kernel@lists.infradead.org, Charulatha V X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Wed, 13 Jul 2011 14:02:15 +0000 (UTC) Simplify omap2_gpio_prepare_for_idle() and omap2_gpio_resume_after_idle() by moving most of the stuff to *_pm_runtime_suspend() and *_pm_runtime_resume(). Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate per GPIO bank instead of operating on entire list every time. Signed-off-by: Tarun Kanti DebBarma Signed-off-by: Charulatha V --- drivers/gpio/gpio-omap.c | 234 ++++++++++++++++++++++++--------------------- 1 files changed, 125 insertions(+), 109 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 47e5e20..32281f6 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -1145,142 +1145,153 @@ static int omap_gpio_resume(struct device *dev) static void omap_gpio_save_context(struct gpio_bank *bank); static void omap_gpio_restore_context(struct gpio_bank *bank); -void omap2_gpio_prepare_for_idle(int off_mode) +static int omap_gpio_runtime_suspend(struct device *dev) { - struct gpio_bank *bank; + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = platform_get_drvdata(pdev); + u32 l1 = 0, l2 = 0; + int j; - list_for_each_entry(bank, &omap_gpio_list, node) { - u32 l1 = 0, l2 = 0; - int j; + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) + clk_disable(bank->dbck); - if (!bank->loses_context) - continue; + /* If going to OFF, remove triggering for all + * non-wakeup GPIOs. Otherwise spurious IRQs will be + * generated. See OMAP2420 Errata item 1.101. */ + if (!(bank->enabled_non_wakeup_gpios)) + goto save_gpio_ctx; - for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) - clk_disable(bank->dbck); + bank->saved_datain = __raw_readl(bank->base + + bank->regs->datain); + l1 = __raw_readl(bank->base + bank->regs->fallingdetect); + l2 = __raw_readl(bank->base + bank->regs->risingdetect); - if (!off_mode) - continue; + bank->saved_fallingdetect = l1; + bank->saved_risingdetect = l2; + l1 &= ~bank->enabled_non_wakeup_gpios; + l2 &= ~bank->enabled_non_wakeup_gpios; - if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) - dev_err(bank->dev, "%s: GPIO bank %d " - "pm_runtime_put_sync failed\n", - __func__, bank->id); + __raw_writel(l1, bank->base + bank->regs->fallingdetect); + __raw_writel(l2, bank->base + bank->regs->risingdetect); + +save_gpio_ctx: + if (bank->get_context_loss_count) + bank->ctx_loss_count = bank->get_context_loss_count(bank->dev); + omap_gpio_save_context(bank); + + return 0; +} + +static int omap_gpio_runtime_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gpio_bank *bank = platform_get_drvdata(pdev); + u32 ctx_lost_cnt_after; + u32 l = 0, gen, gen0, gen1; + int j; + + for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) + clk_enable(bank->dbck); - /* If going to OFF, remove triggering for all - * non-wakeup GPIOs. Otherwise spurious IRQs will be - * generated. See OMAP2420 Errata item 1.101. */ - if (!(bank->enabled_non_wakeup_gpios)) - goto save_gpio_ctx; + if (bank->get_context_loss_count) { + ctx_lost_cnt_after = + bank->get_context_loss_count(bank->dev); + if (ctx_lost_cnt_after != bank->ctx_loss_count || + !ctx_lost_cnt_after) + omap_gpio_restore_context(bank); + } - bank->saved_datain = __raw_readl(bank->base + - bank->regs->datain); - l1 = __raw_readl(bank->base + bank->regs->fallingdetect); - l2 = __raw_readl(bank->base + bank->regs->risingdetect); + if (!(bank->enabled_non_wakeup_gpios)) + return 0; - bank->saved_fallingdetect = l1; - bank->saved_risingdetect = l2; - l1 &= ~bank->enabled_non_wakeup_gpios; - l2 &= ~bank->enabled_non_wakeup_gpios; + __raw_writel(bank->saved_fallingdetect, + bank->base + bank->regs->fallingdetect); + __raw_writel(bank->saved_risingdetect, + bank->base + bank->regs->risingdetect); + l = __raw_readl(bank->base + bank->regs->datain); - __raw_writel(l1, bank->base + bank->regs->fallingdetect); - __raw_writel(l2, bank->base + bank->regs->risingdetect); + /* Check if any of the non-wakeup interrupt GPIOs have changed + * state. If so, generate an IRQ by software. This is + * horribly racy, but it's the best we can do to work around + * this silicon bug. */ + l ^= bank->saved_datain; + l &= bank->enabled_non_wakeup_gpios; -save_gpio_ctx: - if (bank->get_context_loss_count) - bank->ctx_loss_count = - bank->get_context_loss_count(bank->dev); + /* + * No need to generate IRQs for the rising edge for gpio IRQs + * configured with falling edge only; and vice versa. + */ + gen0 = l & bank->saved_fallingdetect; + gen0 &= bank->saved_datain; + gen1 = l & bank->saved_risingdetect; + gen1 &= ~(bank->saved_datain); + + /* FIXME: Consider GPIO IRQs with level detections properly! */ + gen = l & (~(bank->saved_fallingdetect) & + ~(bank->saved_risingdetect)); + /* Consider all GPIO IRQs needed to be updated */ + gen |= gen0 | gen1; + + if (gen) { + u32 old0, old1; + + old0 = __raw_readl(bank->base + + bank->regs->leveldetect0); + old1 = __raw_readl(bank->base + + bank->regs->leveldetect1); + + __raw_writel(old0, bank->base + + bank->regs->leveldetect0); + __raw_writel(old1, bank->base + + bank->regs->leveldetect1); + if (cpu_is_omap24xx() || cpu_is_omap34xx()) { + old0 |= gen; + old1 |= gen; + } - omap_gpio_save_context(bank); + if (cpu_is_omap44xx()) { + old0 |= l; + old1 |= l; + } + __raw_writel(old0, bank->base + + bank->regs->leveldetect0); + __raw_writel(old1, bank->base + + bank->regs->leveldetect1); } + + return 0; } -void omap2_gpio_resume_after_idle(void) +void omap2_gpio_prepare_for_idle(int off_mode) { struct gpio_bank *bank; - list_for_each_entry(bank, &omap_gpio_list, node) { - u32 ctx_lost_cnt_after; - u32 l = 0, gen, gen0, gen1; - int j; + if (!off_mode) + return; - if (!bank->loses_context) + list_for_each_entry(bank, &omap_gpio_list, node) { + if (!bank->mod_usage || !bank->loses_context) continue; - if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) + if (IS_ERR_VALUE(pm_runtime_put_sync(bank->dev) < 0)) dev_err(bank->dev, "%s: GPIO bank %d " - "pm_runtime_get_sync failed\n", + "pm_runtime_put_sync failed\n", __func__, bank->id); + } +} - for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) - clk_enable(bank->dbck); - - if (bank->get_context_loss_count) { - ctx_lost_cnt_after = - bank->get_context_loss_count(bank->dev); - if (ctx_lost_cnt_after != bank->ctx_loss_count || - !ctx_lost_cnt_after) - omap_gpio_restore_context(bank); - } +void omap2_gpio_resume_after_idle(void) +{ + struct gpio_bank *bank; - if (!(bank->enabled_non_wakeup_gpios)) + list_for_each_entry(bank, &omap_gpio_list, node) { + if (!bank->mod_usage || !bank->loses_context) continue; - __raw_writel(bank->saved_fallingdetect, - bank->base + bank->regs->fallingdetect); - __raw_writel(bank->saved_risingdetect, - bank->base + bank->regs->risingdetect); - l = __raw_readl(bank->base + bank->regs->datain); - - /* Check if any of the non-wakeup interrupt GPIOs have changed - * state. If so, generate an IRQ by software. This is - * horribly racy, but it's the best we can do to work around - * this silicon bug. */ - l ^= bank->saved_datain; - l &= bank->enabled_non_wakeup_gpios; - - /* - * No need to generate IRQs for the rising edge for gpio IRQs - * configured with falling edge only; and vice versa. - */ - gen0 = l & bank->saved_fallingdetect; - gen0 &= bank->saved_datain; - - gen1 = l & bank->saved_risingdetect; - gen1 &= ~(bank->saved_datain); - - /* FIXME: Consider GPIO IRQs with level detections properly! */ - gen = l & (~(bank->saved_fallingdetect) & - ~(bank->saved_risingdetect)); - /* Consider all GPIO IRQs needed to be updated */ - gen |= gen0 | gen1; - - if (gen) { - u32 old0, old1; - - old0 = __raw_readl(bank->base + - bank->regs->leveldetect0); - old1 = __raw_readl(bank->base + - bank->regs->leveldetect1); - - __raw_writel(old0, bank->base + - bank->regs->leveldetect0); - __raw_writel(old1, bank->base + - bank->regs->leveldetect1); - if (cpu_is_omap24xx() || cpu_is_omap34xx()) { - old0 |= gen; - old1 |= gen; - } - - if (cpu_is_omap44xx()) { - old0 |= l; - old1 |= l; - } - __raw_writel(old0, bank->base + - bank->regs->leveldetect0); - __raw_writel(old1, bank->base + - bank->regs->leveldetect1); - } + if (IS_ERR_VALUE(pm_runtime_get_sync(bank->dev) < 0)) + dev_err(bank->dev, "%s: GPIO bank %d " + "pm_runtime_get_sync failed\n", + __func__, bank->id); } } @@ -1325,9 +1336,14 @@ static void omap_gpio_restore_context(struct gpio_bank *bank) bank->base + bank->regs->fallingdetect); __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout); } +#else +#define omap_gpio_runtime_suspend NULL +#define omap_gpio_runtime_resume NULL #endif static const struct dev_pm_ops gpio_pm_ops = { + .runtime_suspend = omap_gpio_runtime_suspend, + .runtime_resume = omap_gpio_runtime_resume, .suspend = omap_gpio_suspend, .resume = omap_gpio_resume, };